is set to "1" (enable), either even or odd parity may be selected using the sc0cr bit. the length of the stop bit can be specified using sc0mod2. example: the control register settings for transmitting in the following data format are listed in the following table. transmission direction (transmission rate of 2400bps, @fc =24.576mhz) start bit 0 1 2 3 5 4 6 even parity stop * clocking conditions system clock : high-speed (fc) high-speed clock gear : x 1 (fc) prescaler clock : fperiph/4 (fperiph = fsys) 7 6 5 4 3 2 1 0 pccr ? ? ? ? ? ? ? 1 pcfc ? ? ? ? ? ? ? 1 designates pc0 as the txd0 pin. sc0mod x 0 ? x 0 101 sets the 7-bit uart mode. sc0cr x 1 1 x x x 0 0 adds even parity. br0cr 0 0 1 0 1 0 1 0 sets the data rate to 2400 bps. imc3 ? 1 1 ? 0 100 enables the inttx0 interrupt and sets to level 4 by the <31:24> bits of the 32 bit register. sc0buf * * * * * * * * sets the data to be sent. note: x: don't care - : no change 13.5.3 mode 2 (8-bit uart mode) the 8-bit uart mode can be selected by setting sc0mod0 to "10." in this mode, parity bits can be added and parity enable/disable is controlled using sc0cr . if = "1" (enabled), either even or odd parity can be selected using sc0cr . example: the control register settings for receivi ng data in the following format are as follows: transmission direction (transmission rate of 9600bps, @fc =24.576mhz) start bit 0 1 2 3 5 4 6 odd parity stop 7 * clocking conditions system clock : high-speed (fc) high-speed clock gear : x 1 (fc) prescaler clock : fperiph/4 (fperiph = fsy s )
tmp19a64c1d tmp19a64(rev1.1)- 13-39 main routine settings 7 6 5 4 3 2 1 0 pccr ? ? ? ? ? ? 0 ? pcfc ? ? ? ? ? ? 1 ? designates pc1 as the rxd0 pin. sc0mod ? 0 0 x 1 0 0 1 selects the 8-bit uart mode. sc0cr x 0 1 x x x 0 0 sets odd parity. br0cr 0 0 0 1 0 1 0 1 sets the data rate to 9600 bps. imc3 ? 1 1 ? 0100 enables the intrx0 interrupt and sets to level 4 by the <23:16> bits of the 32 bit register. sc0mod ? ? 1 x ? ? ? ? enables reception of data. an example interrupt routine process intclr 0 0 0 1 1 1 0 0 0 clears the interrupt request. 0x0000_0038 reg. sc0cr and 0x1c if reg. is not "0" then error processing set sc0buf to reg. reads received data. interrupt processing is completed note: x: don't care - : no change performs error check no yes error processing sc0cr=0x1c ? sc0buf data read interrupt process complete interrupt process start intclr=0x38
tmp19a64c1d tmp19a64(rev1.1)- 13-40 13.5.4 mode 3 (9-bit uart) the 9-bit uart mode can be selected by setting sc0mod0 to "11." in this mode, parity bits must be disabled (sc0cr = "0"). the most significant bit (9th bit) is written to b it 7 of the serial mode control register 0 (sc0mod0) for transmit data and it is stored in bit 7 of the serial control register sc0cr upon receiving data. when writing or readin g data to/from the buffers, the most significant bit must be written or read first before writing or reading to/from sc0buf. the stop bit length can be specified using sc0mod2 . wakeup function in the 9-bit uart mode, slave controllers can be operated in the wake-up mode by setting the wake-up function control bit sc0mod0 to "1." in this case, the interrupt intrx0 will be generated only when sc0cr is set to "1." (note) the txd pin of the slave controller must be set to the open drain output mode using the ode register. fig. 13.5.4.1 serial links to use wake-up function txd master slave 1 slave 2 slave 3 rxd txd rxd txd txd rxd rxd
tmp19a64c1d tmp19a64(rev1.1)- 13-41 protocol c select the 9-bit uart mode for the master and slave controllers. d set sc0mod to "1" for the slave contro llers to make them ready to receive data. e the master controller is to send a single frame of data that includes the slave controller select code (8 bits). in this, the most significant bit (bit 8) must be set to "1." slave controller select code start bit 0 1 2 3 5 4 6 stop 7 8 ?1? f every slave controller receives the above data frame; if the code received matches with the controller's own select code, it clears the wu bit to "0." g the master controller transmits data to the desi gnated slave controller (the controller of which sc0mod bit is cleared to "0"). in this, the most significant bit (bit 8) must be set to "0." data ?0? start bit 0 1 2 3 5 4 6 stop 7 bit 8 h the slave controllers with the bit set to "1" ignore the receive data because the most significant bit (bit 8) is set to "0" a nd thus no interrupt (intrx0) is generated. also, the slave controller with the bit set to "0" can transmit data to the master controller to inform that the data has been successfully received. example setting: using the internal clock fsys/2 as the transfer clock, two slave controllers are serially linked as follows: txd master slave 1 slave 2 select code 00000001 rxd txd rxd txd rxd select code 00001010
tmp19a64c1d tmp19a64(rev1.1)- 13-42 c master controller setting main routine pccr ? ? ? ? ? ? 01 pcfc ? ? ? ? ? ? 11 designates pc0/pc1 as the txd0/rxd0 pins, respectively. ? 1 1 ? 0101 enables the intrx0 interrupt and sets to level 5 by the <23:16> bits of the 32 bit register. imc3 ? 1 1 ? 0100 enables the inttx0 interrupt and sets to level 4 by the <31:24> bits of the 32 bit register. sc0mod0 1 0 1 0 1 1 1 0 sets the 9-bit uart mode and fsys/2 transfer clock. sc0buf 0 0 0 0 0 0 0 1 sets the select code of slave 1. interrupt routine (inttx0) intclr 0 0 0 1 1 1 1 0 0 clears the interrupt request. (0x0000_003c) sc0mod0 0 ? ? ? ? ? ? ? sets tb8 to "0." sc0buf * * * * * * * * sets the data to be sent. interrupt processing is completed. d slave controller setting main routine pccr ? ? ? ? ? ? 01 pcfc ? ? ? ? ? ? 11 designates pc0 as txd (open drain output) and pc1 as rxd. pcode ? ? ? ? ? ? ? 1 ? 1 1 ? 0110 enables inttx0 and intrx0. imc3 ? 1 1 ? 0101 sc0mod0 0 0 1 1 1 1 1 0 sets the 9-bit uart mode and f sys /2 transfer clock and sets to "1." interrupt routine (intrx0) intclr 0 0 0 1 1 1 0 0 0 clears the interrupt request. reg. sc0buf if reg. = select code, then sc0mod0 ? ? ? 0 ? ? ? ? clears to "0."
tmp19a64c1d tmp19a64(rev1.1)- 14-1 14. serial bus interface (sbi) the tmp19a64 contains a serial bus interface (sbi) channel, which has the following two operating modes: ? i 2 c bus mode (with multi-master capability) ? clock-synchronous 8-bit sio mode in the i 2 c bus mode, the sbi is connected to external devi ces via pf0 (sda) and pf1 (scl). in the clock- synchronous 8-bit sio mode, the sbi is connected to external devices via pf2 (sck), pf0 (so) and pf1 (si). the following table shows the programming required to put the sbi in each operating mode. pfode pfcr pffc i2c bus mode 11 x11 011 clock-synchronous 8-bit sio mode xx 101 (clock output) 001 (clock input) 111 x: don't care 14.1 configuration the configuration is shown in fig. 14.1. fig. 14.1 sbi block diagram i 2 c bus clock synchroni- zation + control shift register sbicr2/ sbisr sbidbr intsbi interrupt request fsys/4 sbi control register 2/ sbi status register i 2 c bus address register sbi data buffer register sbi control registers 0 and 1 sbi baud rate registers 0 and 1 sda so si scl sck pf2 pf0 pf1 (sck) (so/sda) (si/scl) sio clock control frequency divider transfer control circuit sbicr0,1 sbibr0, 1 i2car noise canceller i 2 c bus data control sio data control input/ output control noise canceller
tmp19a64c1d tmp19a64(rev1.1)- 14-2 14.2 control the following registers control the serial bus interface and provide its status information for monitoring. ? serial bus interface control register 0 (sbicr0) ? serial bus interface control register 1 (sbicr1) ? serial bus interface control register 2 (sbicr2) ? serial bus interface buffer register (sbidbr) ? i 2 c bus address register (i2car) ? serial bus interface status register (sbisr) ? serial bus interface baud rate register 0 (sbibr0) the functions of these registers vary, depending on the mode in which the sbi is operating. for a detailed description of the registers, re fer to "14.5 control in the i 2 c bus mode" and "14.7 control in the clock- synchronous 8-bit sio mode." 14.3 i 2 c bus mode data formats fig. 14.3 shows the data formats used in the i 2 c bus mode. fig. 14.3 i 2 c bus mode data formats note: s: start condition w / r : direction bit ack: acknowledge bit p: stop condition r / w r / w s (a) addressing format (b) addressing format (with repeated start condition) (c) free data format (master-transmitter to slave-receiver) slave address data p s s sp p 8 bits 1to 8bits 1 once repeated 1to 8bits a c k slave address data data once once a c k a c k 8 bits 1to 8bits 8bits 1to 8bits 11 1 1 1 1 8bits 1 to 8 bits 1to 8bits data data data data a c k 1 1 1 slave address repeated once repeated repeated r / w a c k a c k a c k a c k a c k a c k
tmp19a64c1d tmp19a64(rev1.1)- 14-3 14.4 control registers in the i 2 c bus mode the following registers control the se rial bus interface (sbi) in the i 2 c bus mode and provide its status information for monitoring. serial bus interface control register 0 7 6 5 4 3 2 1 0 bit symbol sbien read/write r/w r after reset 0 0 0 0 0 0 0 0 function sbi operation 0: disable 1: enable : to use the sbi, enable the sbi operat ion ("1") before setting each register in the sbi module. (note) bits 0 to 6 of sbicro are read as "0." fig. 14.4.1 i 2 c bus mode register sbicr0 (0xffff_f257)
tmp19a64c1d tmp19a64(rev1.1)- 14-4 serial bus interface control register 1 7 6 5 4 3 2 1 0 bit symbol bc2 bc1 bc0 ack sck2 sck1 sck0/ swrmon read/write r/w r/w r r/w r/w after reset 0 0 0 0 1 0 0 1 function select the number of bits per transfer (note 1) acknow- ledgment clock 0: not generate 1: generate select internal scl output clock frequency (note 2) and reset monitor on writing : select internal scl output clock frequency 000 001 010 011 100 101 110 111 n=5 n=6 n=7 n=8 n=9 n=10 n=11 265 khz 201 khz 136 khz 83 khz 46 khz 25 khz 13 khz reserved system clock : fsys (=54 mhz) clock gear : fc/1 frequency = [hz] on reading : softwa re reset status monitor 0 software reset operation is in progress. 1 software reset operation is not in progress. select the number of bits per transfer when = 0 when = 1 number of clock cycles data length number of clock cycles data length 000 001 010 011 100 101 110 111 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 9 2 3 4 5 6 7 8 8 1 2 3 4 5 6 7 (note 1) clear to "000" before switchi ng the operation mode to the clock-synchronous 8-bit sio mode. (note 2) for details on the scl line clock frequency, refer to "14.5.3 serial clock." (note 3) after a reset, the bit is read as "1." however, if the sio mode is selected at the sbicr2 register, the initial value of the bit is "0." fig. 14.4.2 i 2 c bus mode register sbicr1 (0xffff_f250) fsys/2 2 n + 70
tmp19a64c1d tmp19a64(rev1.1)- 14-5 serial bus interface control register 2 7 6 5 4 3 2 1 0 bit symbol mst trx bb pin sbim1 sbim0 swrst1 swrst0 read/write w w w after reset 0 0 0 1 0 0 0 0 function select master/slave 0: slave 1: master select transmit/ receive 0: receive 1: transmit start/stop condition generation 0: stop condition generated 1: start condition generated clear intsbi interrupt request 0: ? 1: clear interrupt request select serial bus interface operating mode (note 2) 00: port mode 01: sio mode 10: i 2 c bus mode 11: (reserved) software reset generation write "10" followed by "01" to generate a reset. select serial bus interf ace operating mode (note 2) 00 port mode (serial bus in terface output disabled) 01 clock-synchronous 8-bit sio mode 10 i 2 c bus mode 11 (reserved) (note 1) reading this register causes it to function as the sbisr register. (note 2) ensure that the bus is free before switching the operating mode to the port mode. ensure that the port is at the "h" level before switching the operating mode from the port mode to the i 2 c bus or clock-synchronous 8-bit sio mode. fig. 14.4.3 i 2 c bus mode register table 14.4.4 base clock resolution @fsys = 54 mhz clock gear value base clock resolution 000 (fc) fsys/2 2 (0.07 s) 100 (fc/2) fsys/2 3 (0.14 s) 110 (fc/4) fsys/2 4 (0.28 s) 111 (fc/8) fsys/2 5 (0.58 s) sbicr2 (0xffff_f253)
tmp19a64c1d tmp19a64(rev1.1)- 14-6 serial bus interface status register 7 6 5 4 3 2 1 0 bit symbol mst trx bb pin al aas ad0 lrb read/write r after reset 0 0 0 1 0 0 0 0 function master/slave selection monitor 0: slave 1: master transmit/ receive selection monitor 0: receive 1: transmit i 2 c bus state monitor 0: free 1: busy intsbi interrupt request monitor 0: interrupt request generated 1: interrupt request cleared arbitration lost detection 0: ? 1: detected slave address match detection 0: ? 1: detected general call detection 0: ? 1: detected last received bit monitor 0: "0" 1: "1" last received bit monitor 0 the last bit received was "0." 1 the last bit received was "1." addressed as slave 0 ? 1 addressed as slave or general call detected arbitration lost 0 ? 1 arbitration was lost to another master (note) writing to this register causes it to function as sbicr2. fig. 14.4.5 i 2 c bus mode register sbisr (0xffff_f253)
tmp19a64c1d tmp19a64(rev1.1)- 14-7 serial bus interface baud rate register0 7 6 5 4 3 2 1 0 bit symbol i2sbi read/write r r/w r r/w after reset 1 0 1 1 1 1 1 0 function idle 0: stop 1: operate make sure that you write "0." operation in the idle mode 0stop 1operate serial bus interface data buffer register 7 6 5 4 3 2 1 0 bit symbol db7 db6 db5 db4 db3 db2 db1 db0 read/write r (receive)/w (transmit) after reset 0 (note) transmit data must be written to this register, with bit 7 being the most-significant bit (msb). i 2 c bus address register 7 6 5 4 3 2 1 0 bit symbol sa6 sa5 sa4 sa3 sa2 sa1 sa0 als read/write r/w after reset 0 0 0 0 0 0 0 0 function set the slave address when the sbi acts as a slave device. specify address recognition mode specify address recognition mode 0 recognizes the slave address. 1 does not recognize slave address. fig. 14.4.6 i 2 c bus mode register sbibr0 (0xffff_f254) sbidbr (0xffff_f251) i2car (0xffff_f252)
tmp19a64c1d tmp19a64(rev1.1)- 14-8 14.5 control in the i 2 c bus mode 14.5.1 setting the acknowledgement mode setting sbicr1 to "1" selects the acknowledge mode. when operating as a master, the sbi adds one clock for acknowledgment signals. as a transmitte r, the sbi releases the sda pin during this clock cycle to receive acknowledgment signals from the receiver. as a receiver, the sbi pulls the sda pin to the "l" level during this clock cycle and generates acknowledgment signals. setting to "0" selects the non-acknowledgment mode. when operating as a master, the sbi does not generate clock for acknowledgement signals. 14.5.2 setting the number of bits per transfer sbicr1 specifies the numb er of bits of the next data to be transmitted or received. under the start condition, is set to "000," causing a slave address and the direction bit to be transferred in a packet of eight bits. at other times, keeps a previously programmed value. 14.5.3 serial clock c clock source sb sbicr1 specifies the maximum frequency of the serial clock to be output from the scl pin in the master mode. fig. 14.5.3.1 clock source the highest speeds in the standard and high-speed modes are specified to 100 khz and 400 khz respectively in the communications standards. note that the internal scl clock frequency is determined by the fsys used and the calculation formula shown above. t high t low 1/fscl t low = 2 n-1 /(fsys/2) + 58/(fsys/2) t high = 2 n-1 /(fsys/2) + 12/(fsys/2) fscl = 1/(t low + t high ) sbi0cr1 n 000 001 010 011 100 101 110 5 6 7 8 9 10 11 = fsys/2 2 n + 70
tmp19a64c1d tmp19a64(rev1.1)- 14-9 d clock synchronization the i 2 c bus is driven by using the wired-and connection du e to its pin structure. the first master that pulls its clock line to the "l" level overrides other masters producing the "h" level on their clock lines. this must be detected and responded by the masters producing the "h" level. clock synchronization assures correct data transfer on a bus that has two or more masters. for example, the clock synchron ization procedure for a bus with two masters is shown below. fig. 14.5.3.2 example of clock synchronization at point a, master a pulls its internal scl output to the "l" level, bringing the scl bus line to the "l" level. master b detects this transition, resets its "h" level period counter, and pulls its internal scl output level to the "l" level. master a completes counting of its "l" level period at point b, and brings its internal scl output to the "h" level. however, master b still keeps the scl bus line at the "l" level, and master a stops counting of its "h" level period counting. after master a det ects that master b brings its internal scl output to the "h" level and brings the scl bus line to the "h" le vel at point c, it starts counting of its "h" level period. this way, the clock on the bus is determined by th e master with the shortest "h" level period and the master with the longest "l" level peri od among those connected to the bus. 14.5.4 slave addressing and address recognition mode when the sbi is configured to op erate as a slave device, the slave address and must be set at i2car. setting to "0" selects the address recognition mode 14.5.5 configuring the sbi as a master or a slave setting sbicr2 to "1" configures the sbi to operate as a master device. setting to "0" configures the sbi as a slave de vice. is cleared to "0" by the hardware when the stop condition has been detected on the bus or when arbitration has been lost. internal scl output (master a) internal scl output (master b) scl line reset high-level period counting wait for high-level period counting start high-level period counting a b c
tmp19a64c1d tmp19a64(rev1.1)- 14-10 14.5.6 configuring the sbi as a transmitter or a receiver setting sbicr2 to "1" configures the sbi as a transmitter. setting to "0" configures the sbi as a receiver. in the slave mode, the sbi receives the direction bit ( w r/ ) from the master device on the following occasions: ? when data is transmitted in the addressing format ? when the received slave address ma tches the value specified at i2ccr ? when a general-call address is received; i.e., th e eight bits following the start condition are all zeros if the value of the direction bit ( w r/ ) is "1," is set to "1" by the hardware. if the bit is "0," is set to "0." as a master device, the sbi receives acknowledgement from a slave device. if the directio n bit of "1" is transmitted, is set to "0" by th e hardware. if the direction bit is "0," changes to "1." if the sbi does not receive acknowledgement, retains the previous value is cleared to "0" by the hard ware when the stop co ndition has been detected on the bus or when arbitration has been lost. 14.5.7 generating start and stop conditions when sbisr is "0," writing "1" to sbicr2 causes th e sbi to generate the start condition on the bus and out put 8-bit data. must be set to "1" in advance. fig. 14.5.7.1 generating the start condition and a slave address when is "1," writing "1" to and "0" to causes th e sbi to start a sequence for generating the stop condition on the bus. the contents of should not be altered until the stop co ndition appears on the bus. fig. 14.5.7.2 generating the stop condition sbisr can be read to check the bus state. is set to "1" when the star t condition is detected on the bus (the bus is busy), and set to "0" when the stop condition is detected (the bus is free). scl line start condition a6 slave address and direction bit a cknowledgment signal 1 sda line 234567 8 9 a5 a4 a3 a2 a1 a0 r/w stop condition scl line sda line
tmp19a64c1d tmp19a64(rev1.1)- 14-11 14.5.8 interrupt service request and release when a serial bus interface interrupt request (intsbi) is generated, sbicr2 is cleared to "0." while is "0," the sbi pulls the scl line to the "l" level. after transmission or reception of on e data word, is cleared to "0." it is set to "1" when data is written to or read from sbidbr. it takes a period of t low for the scl line to be released after is set to "1." in the address recognition mode ( = "0"), is cleared to "0" when the received slave address matches the value specified at i2car or when a gene ral-call address is receive d; i.e., the eight bits following the start condition are all zer os. when the program writes "1" to sbicr2, it is set to "1." however, writing "0" does clear this bit to "0." 14.5.9 serial bus interface operating modes sbicr2 selects an operating mode of the serial bus interf ace. must be set to "10" to configure the sbi for the i 2 c bus mode. make sure that the bus is free before switching the operating mode to the port mode. 14.5.10 lost-arbitration detection monitor the i 2 c bus has the multi-master capability (there are two or more masters on a bus), and requires the bus arbitration procedure to ensu re correct data transfer. a master that attempts to generate the start condition while the bus is busy lose s bus arbitration, with no start condition occurring on th e sda and scl lines. the i 2 c-bus arbitration takes place on the sda line. the arbitration procedur e for two masters on a bus is shown below. up until point a, master a and master b output the same data. at point a, master a output s the "l" level and master b outputs the "h" level. then master a pulls the sda bus line to the "l" le vel because the line has the wired-and connection. when the scl line goes high at point b, the slave device reads the sda lin e data, i.e., data transmitted by master a. at this time, data transmitted by master b becomes invalid. in other words, master b loses arbitration. master b releases its sda pin, so that it does not affect the data transfer initiated by another master. if two or more masters have transmitted exactly the same first data word , the arbitra tion procedure continues with the second data word. fig. 14.5.10.1 lost arbitration loses arbitration and sets the internal sda output to "1." scl line internal sda output (master a) internal sda output (master b) sda line ab
tmp19a64c1d tmp19a64(rev1.1)- 14-12 a master compares the sda bus line le vel and the internal sda output level at the rising of the scl line. if there is a difference between these two values, the mast er loses arbitration and se ts sbi0sr to "1." when is set to "1," sbisr are clea red to "0," causing the sb i to operate as a slave receiver. is cleared to "0" when data is written to or read from sbidbr or data is written to sbicr2. fig. 14.5.10.2 example of mast er b losing arbitration (d7a = d7b, d6a = d6b) 14.5.11 slave address match detection monitor when the sbi operates as a slave device in the address recognition mode (i2ccr = "0"), sbisr is set to "1" on re ceiving the general-call a ddress or the slave address that matches the value specified at i2ccr. when is "1 ," is set to "1" when the fi rst data word has been received. is cleared to "0" when data is written to or read from sbidbr. 14.5.12 general-call detection monitor when the sbi operates as a slave device, sbisr is set to "1" when it receives the general-call address; i.e., the eight b its following the start cond ition are all zeros. is cleared to "0" when the start or stop condition is detected on the bus. 14.5.13 last received bit monitor sbisr is set to the sda line value that wa s read at the rising of the scl line. in the acknowledgment mode, reading sbisr immediat ely after generation of the intsbi interrupt request causes ack signal to be read. clock output stops here 1 internal sda output is held high because master b has lost arbitraiton. a ccess to sbidbr or sbicr2 internal scl output internal sda output internal sda output internal scl output master a master b 23456789 1 2 34 d7a d6b d5a d4a d3a d2a d1a d0a d7a? d6a? d5a? d4a? 1 234 d7b d6a
tmp19a64c1d tmp19a64(rev1.1)- 14-13 14.5.14 software reset if the serial bus interface circuit locks up due to ex ternal noise, it can be initia lized by using a software reset. writing "10" followed by "01" to sb icr2 generates a reset signal that initializes the serial bus interface circuit. after a reset, all control registers and status fl ags are initialized to their reset values. when the serial bus interface is initialized, is automatically cleared to "0." (note) after a software reset, the operating mode is also reset from the i 2 c mode to the synchronous communication mode. 14.5.15 serial bus interface data buffer register (sbidbr) reading or writing sbidbr initiates reading received data or writing transmitted data. when the sbi is acting as a master, setting a slave address and a directio n bit to this register ge nerates the start condition. 14.5.16 i 2 c bus address register (i2car) when the sbi is configured as a slave device, the i2car bit is used to specify a slave address. if i2c0ar is set to "0," the sbi recognizes a slave address transmitted by the master device and receives data in the addressing format. if is set to "1," the sbi does not recognize a slave address and receives data in the free data format. 14.5.17 idle setting register (sbibr0) the sbibr0 register determines if the sbi operates or not when it enters the idle mode. this register must be programmed before executing an instruction to switc h to the standby mode.
tmp19a64c1d tmp19a64(rev1.1)- 14-14 14.6 data transfer procedure in the i 2 c bus mode 14.6.1 device initialization first, program sbicr1 by writing "0" to bits 7 to 5 and bit 3 in sbicr1. next, program i2car by specifying a slave address at and an address recogn ition mode at . ( must be set to "0" when using the addressing format.) next, program sbicr2 to initially configure the sbi in the slave receiver mode by writing "0" to , "1" to , "10" to and "0" to bits 1 and 0. 7 6 5 4 3 2 1 0 sbicr1 0 0 0 x 0 x x x specifies ack and scl clock. i2car x x x x x x x x specifies a slave address and an address recognition mode. sbicr2 0 0 0 1 1 0 0 0 configures the sbi as a slave receiver. ( note) x: don?t care 14.6.2 generating the start condition and a slave address c master mode in the master mode, the following st eps are required to generate the start condition and a slave address. first, ensure that the bus is free ( = "0"). then, write "1" to sbicr1 to select the acknowledgment mode. write to sbidbr a slave ad dress and a direction b it to be transmitted. when = "0," writing "1111" to sbic r2 gene rates the start condition on the bus. following the start condition, the sbi generates nine clocks from the scl pin. the sbi outputs the slave address and the di rection bit specified at sbidbr with the first eight clocks, and releases the sda line in the ninth clock to receive an acknowledgment signal from the slave device. the intsbi interrupt request is gene rated on the falling of the ninth clock, and is cleared to "0." in the master mode, the sbi holds the scl line at th e "l" level while is "0." changes its value according to the transmitted di rection bit at generation of the in tsbi interrupt re quest, provided that an acknowledgment signal has been returned from the slave device. settings in main routine 7 6 5 4 3 2 1 0 reg. sbisr reg. reg. e 0x20 if reg. 0x00 ensures that the bus is free. then sbicr1 x x x 1 0 x x x selects the acknow ledgement mode. sbidr1 x x x x x x x x specifies the desired slav e address and direction. sbicr2 1 1 1 1 1 0 0 0 generates the start condition. example of intsbi interrupt routine intclr 0x50 clears the interrupt request. processing end of interrupt
tmp19a64c1d tmp19a64(rev1.1)- 14-15 slave mode in the slave mode, the sbi receives th e start conditio n and a slave address. after receiving the start condition from the master device, the sbi receives a slave address and a direction bit from the master device during the fi rst eight clocks on the scl line. if the received address matches its slave address sp ecified at i2car or is equal to the general-call address, the sbi pulls the sda line to the "l" level during the ninth clock and outputs an acknowledgment signal. the intsbi interrupt request is gene rated on the falling of the ninth clock, and is cleared to "0." in the slave mode, the sbi holds the scl lin e at the "l" level while is "0." (note) the user can only use a dma transfer: ? when there is only one master and only one slave and ? continuous transmission or reception is possible. fig. 14.6.2.1 generation of the st art condition and a slave address 14.6.3 transferring a data word at the end of a data word transfer , the intsbi interrupt is generated to test to determine whether the sbi is in the master or slave mode. c master mode ( = "1") test to determine whether the sbi is configured as a transmitter or a receiver. transmitter mode ( = "1") test . if is "1," that means the recei ver requires no further data. the master then generates the stop conditio n as described later to stop transmission. if is "0," that means the receiver requires furt her data. if the next data to be transmitted has eight bits, the data is written into sbidbr. if th e data has different leng th, and are programmed and the transmit data is written into sbidbr. writing the data makes to"1," causing the scl pin to generate a serial clock for transfer of a next data word, and the sda pin to transfer the data word. af ter the transfer is complete d, the intsbi interrupt re quest is generated, is set to "0," and the scl pin is pulled to the "l" level. to transmit more data words, test again and repeat the above procedure. scl start condition a6 slave address + direction bit a cknowledgement from slave 1 sda 2 345678 9 a5 a4 a3 a2 a1 a0 w r/ intsbi interrupt request ack master to slave slave to master
tmp19a64c1d tmp19a64(rev1.1)- 14-16 intsbi interrupt if mst = 0 then go to the slave-mode processing if trx = 0 then go to the receiver-mode processing if lrb = 0 then go to processing for generating the stop condition sbicr1 x x x x 0 x x x specifies the number of bits to be transmitted and specify whether ack is required. sbidbr x x x x x x x x writes the transmit data. end of interrupt processing (note) x: don?t care fig. 14.6.3.1 = "000" and = "1" (transmitter mode) receiver mode ( = "0") if the next data to be transmitted has eight bits, the transmit data is written into sbidbr. if the data has different length, and are programmed and the received data is read from sbidbr to release the scl line. (the data read immediately af ter transmission of a slave address is undefined.) on reading the data, is set to "1," and the serial clock is outp ut to the scl pin to transfer the next data word. in the last bit, when the acknowle dgment signal becomes the "l" level, "0" is output to the sda pin. after that, the intsbi interrupt re quest is generated, and is cleared to "0," pulling the scl pin to the "l" level. each time the received data is read from sbidbr, one-word transfer clock and an acknowledgement signal are output. fig. 14.6.3.2 = "000" and = "1" (receiver mode) scl pin write to sbi0dbr d7 a cknowledgment signal from receiver 1 sda pin 2 345678 9 d6 d5 d4 d3 d2 d1 intsbi interrupt request ack master to slave slave to master d0 scl d7 a cknowledgment signal to transmitter 1 sda 2 345678 9 d6 d5 d4 d3 d2 d1 intsbi interrupt request ack master to slave slave to master d0 read the received data next d7
tmp19a64c1d tmp19a64(rev1.1)- 14-17 to terminate the data transmission from the transmitter, must be set to "0" immediately before reading the second to last data word. this disables generation of an acknowledgment clock for the last data word. when th e transfer is completed, an interrupt request is genera ted. after the interrupt processing, must be set to "001" and the data must be read so that a clock is generated for 1- bit transfer. at this time, the ma ster receiver holds the sd a bus line at the "h" level, which signals the end of transfer to the transmitter as an acknowledgment signal. in the interrupt proce ssing for terminating the rece ption of 1-bit data, the stop condition is generated to terminate the data transfer. fig. 14.6.3.3 terminating data transm ission in the master receiver mode example: when receiving n data words intsbi interrupt (after data transmission) 7 6 5 4 3 2 1 0 sbicr1 x x x x 0 x x x sets the number of bits of da ta to be received and specify whether ack is required. reg. sbi0cbr reads dummy data. end of interrupt intsbi interrupt (first to (n-2)th data reception) 7 6 5 4 3 2 1 0 reg. sbidbr reads the first to (n-2)th data words. end of interrupt intsbi interrupt ( (n-1 )th data reception) 7 6 5 4 3 2 1 0 sbi0cr1 x x x 0 0 x x x disables generation of acknowledgement clock. reg. sbidbr reads the (n-1)th data word. end of interrupt intsbi interrupt (n th data reception) 7 6 5 4 3 2 1 0 sbi0cr1 0 0 1 0 0 x x x generates a clock for 1-bit transfer. reg. sbidbr reads the nth data word. end of interrupt intsbi interrupt (after co mpleting data reception) processing to generate the stop condition terminates the data transmission. end of interrupt (note) x: don?t care scl d7 a cknowledgment signal h to transmitter 1 sda 2 345678 1 d6 d5 d4 d3 d2 d1 intsbi interrupt request master to slave slave to master d0 read out the received data after clearing to "0." 9 read out the received data after setting to "001."
tmp19a64c1d tmp19a64(rev1.1)- 14-18 d slave mode ( = "0") in the slave mode, the sbi generates the intsbi in terrupt request on four o ccasions: 1) when the sbi has received any slave address from the master, 2) wh en the sbi has received a general-call address, 3) when the received slave address matches its own ad dress, and 4) when a data transfer has been completed in response to a general-ca ll. also, if the sbi loses arbitra tion in the master mode, it switches to the slave mode. upon the completion of data word transfer in whic h arbitration is lost, the intsbi interrupt request is ge nerated, is cleared to "0," and the scl pin is pulled to the "l" level. when data is written to or read from sb idbr or when is set to "1," the scl pin is released after a period of t low . in the slave mode, the normal slave mode processing or the processing as a result of lost arbitration is carried out. sbisr , , and are tested to determine the processing required. table 14.6.3.4 shows the slave mode st ates and required processing. example: when the received slave address matches the sbi's own address and the direction bit is "1" in the slave receiver mode intsbi interrupt if trx = 0 then go to other processing if al = 1 then go to other processing if aas = 0 then go to other processing sbicr1 x x x 1 0 x x x sets the number of bits to be transmitted. sbidbr x x x x 0 x x x sets the transmit data. (note) x: don?t care
tmp19a64c1d tmp19a64(rev1.1)- 14-19 table 14.6.3.4 processing in slave mode state processing 1 1 0 arbitration was lost while the slave address was being transmitted, and the sbi received a slave address with the direction bit "1" transmitted by another master. 1 0 in the slave receiver mode, the sbi received a slave address with the direction bit "1" transmitted by the master. set the number of bits in a data word to and write the transmit data into sbi0dbr. 1 0 0 0 in the slave transmitter mode, the sbi has completed a transmission of one data word. test lrb. if it has been set to "1," that means the receiver does not require further data. set to 1 and reset to 0 to release the bus. if has been reset to "0," that means the receiver requires further data. set the number of bits in the data word to and write the transmit data to the sbidbr. 1 1/0 arbitration was lost while a slave address was being transmitted, and the sbi received either a slave address with the direction bit "0" or a general- call address transmitted by another master. 1 0 0 arbitration was lost while a slave address or a data word was being transmitted, and the transfer terminated. 1 1/0 in the slave receiver mode, the sbi received either a slave address with the direction bit "0" or a general-call address transmitted by the master. read the sbidbr (a dummy read) to set to 1, or write "1" to . 0 0 0 1/0 in the slave receiver mode, the sbi has completed a reception of a data word. set the number of bits in the data word to and read the received data from sbidbr.
tmp19a64c1d tmp19a64(rev1.1)- 14-20 14.6.4 generating the stop condition when sbisr is "1," writing "1 " to sbicr2 an d "0" to causes the sbi to start a sequence for generating the stop condition on the bus. do not alter the contents of until the stop cond ition appears on the bus. if another device is holding down the scl bus line, the sbi waits until the scl line is released. after that, the sda pin goes high, causing the stop condition to be generated. 7 6 5 4 3 2 1 0 sbicr2 1 1 0 1 1 0 0 0 generates the stop condition. fig. 14.6.4.1 generating the stop condition scl pin sda pin (read) stop condition ?1? ?1? ?0? ?1?
tmp19a64c1d tmp19a64(rev1.1)- 14-21 14.6.5 repeated start procedure repeated start is used when a master device changes the data transfer directio n without terminating the transfer to a slave device. the procedure of generatin g a repeated start in the master mode is described below. first, set sbicr2 to "0" and write "1" to to rel ease the bus. at this time, the sda pin is held at the "h" level and the scl pin is re leased. because no stop condition is generated on the bus, other devices think that the bus is busy. then , test sbisr and wait until it becomes "0" to ensure that the scl pin is released . next, test and wait until it be comes "1" to ensure that no other device is pulling the scl bus line to th e "l" level. once the bus is determ ined to be free this way, use the steps described above in (2) to generate the start condition. to satisfy the setup time of repeated start, at least 4.7- s wait period (in the standard mode) must be created by the software after the bus is determined to be free. 7 6 5 4 3 2 1 0 sbicr2 0 0 0 1 1 0 0 0 releases the bus. if sbisr 0 checks that the scl pin is released. then if sbisr 1 checks that no other device is pulling the scl pin to the "l" level. then 4.7 s wait sbicr1 x x x 1 0 x x x selects the acknowledgment mode. sbidbr x x x x x x x x sets the desired slave address and direction. sbicr2 1 1 1 1 1 0 0 0 generates the start condition. (note) x: don't care (note) do not write to "0" when it is "0." (repeated start cannot be done.) fig. 14.6.5.1 timing chart of generating a repeated start ?0? ?0? ?0? ?1? ?1? ?1? ?1? ?1? scl (bus) scl pin sda pin 4.7 s (min.) start condition 9
tmp19a64c1d tmp19a64(rev1.1)- 14-22 14.7 control in the clock-sy nchronous 8-bit sio mode the following registers control the seri al bus interface in the clock-synchronous 8-bit sio mode and provide its status information for monitoring. serial bus interface control register 0 7 6 5 4 3 2 1 0 bit symbol sbien read/write r/w r after reset 0 0 0 0 0 0 0 0 function sbi operation 0: disable 1: enable : to use the sbi, enable the sbi operati on ("1") before setting each register of sbi module. (note) bits 0 to 6 of sbicro are read as "0." serial bus interface control register 1 7 6 5 4 3 2 1 0 bit symbol sios sioinh siom1 siom0 sck2 sck1 sck0 read/write r/w r r/w r/w after reset 0 0 0 0 1 0 0 1 function start transfer 0: stop 1: start abort transfer 0: continue 1: abort select transfer mode 00: transmit mode 01: (reserved) 10: transmit/receive mode 11: receive mode select serial clock frequency on writing : select serial clock frequency 000 001 010 011 100 101 110 n = 4 n = 5 n = 6 n = 7 n = 8 n = 9 n =10 1.69 844 422 211 105 53 26 mhz khz khz khz khz khz khz system clock : fsys (=54 mhz) clock gear : fc/1 frequency = [hz] 111 ? external clock (note) set to "0" and to "1" before programming the transfer mode and the serial clock. (note) after a reset, the bit is read as "1." if the sio mode is selected at the sbicr2 register, the initial value of the bit becomes "0." sbicr1 (0xffff_f250) sbicr0 (0xffff_f257) fs y s/2 2 n
tmp19a64c1d tmp19a64(rev1.1)- 14-23 serial bus interface data buffer register 7 6 5 4 3 2 1 0 bit symbol db7 db6 db5 db4 db3 db2 db1 db0 read/write r (receive)/w (transmit) after reset 0 fig. 14.7.1.1 sio mode registers serial bus interface control register 2 7 6 5 4 3 2 1 0 bit symbol sbim1 sbim0 read/write r w r after reset 1 1 1 1 0 0 1 1 function select serial bus interface operating mode 00: port mode 01: clock-synchronous 8-bit sio mode 10: i 2 c bus mode 11: (reserved) serial bus interface register 7 6 5 4 3 2 1 0 bit symbol siof sef read/write r r r after reset 1 1 1 1 0 0 1 1 function serial transfer status monitor 0: terminated 1: in progress shift operation status monitor 0: terminated 1: in progress serial bus interface baud rate register 0 7 6 5 4 3 2 1 0 bit symbol i2sbi read/write r r/w r r/w after reset 1 0 1 1 1 1 1 0 function idle 0: stop 1: operate make sure that you write "0." fig. 14.7.1.2 sio mode registers sbidbr (0xffff_f251) sbicr2 (0xffff_f253) sbisr (0xffff_f253) sbibr0 (0xffff_f254)
tmp19a64c1d tmp19a64(rev1.1)- 14-24 14.7.1 serial clock c clock source internal or external clocks can be se lected by programming sbicr1 . internal clocks in the internal clock mode, one of the seven frequenc ies can be selected as a serial clock, which is output to the outside through the sck pin. at the beginning of a transfer, the sck pin output becomes the "h" level. if the program cannot keep up with th is serial clock rate in writing the transmit data or reading the received data, the sbi automatically enters a wait pe riod. during this period, the serial clock is stopped automatically and the next shift operation is su spended until the proce ssing is completed. fig. 14.7.1.3 automatic wait external clock ( = "111") the sbi uses an external clock supplied from the outside to the sck pin as a serial clock. for proper shift operations, the serial clock at the "h " and "l" levels must have the pulse widths as shown below. fig. 14.7.1.4 maximum transfer frequency of external clock input sck pin output so pin output write the transmit data 3 1 7 2 8 1 2 6 7 8 1 2 3 c 0 a b c automatic wait a 0 a 1 a 2 a 5 a 6 a 7 b 0 b 5 b 6 b 7 c 1 c 2 b 1 b 4 t sckh t sckl , t sckh > 8/fsys sck pin t sck
tmp19a64c1d tmp19a64(rev1.1)- 14-25 d shift edge leading-edge shift is used in transmission. trailing-edge shift is used in reception. leading-edge shift data is shifted at the leading edge of the serial clock (or the falling edge of the sck pin input/output). trailing-edge shift data is shifted at the trailing edge of the se rial clock (or the rising edge of the sck pin input/output). fig. 14.7.1.5 shift edge bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 76543210 * 7654321 ** 765432 *** 76543 **** 7654 ***** 765 ****** 76 ****** 7 so pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 6543210 * 543210 ** 0 ******* 10 ****** 210 ***** 3210 **** 43210 *** ******** 76543210 sck pin shift register sck pin si pin shift register (a) leading-edge shift (b) trailing-edge shift (note) *: don't care
tmp19a64c1d tmp19a64(rev1.1)- 14-26 14.7.2 transfer modes the transmit mode, the receive mode or the transm it/receive mode can be selected by programming sbicr1 . c 8-bit transmit mode set the control register to the transmit m ode and write the transmit data to sbidbr. after writing the transmit data, writin g "1" to sbicr1 starts the transmission. the transmit data is moved from sbidbr to a shift register and out put to the so pin, with the least-significant bit (lsb) first, in synchronization with the serial clock. once the transm it data is transfer red to the shift register, sbidbr becomes empty, and the intsbi (buffer-empty) interrupt is generated, requesting the next transmit data. in the internal clock mode, the serial clock will be st opped and automatically ente r the wait state, if next data is not loaded after the 8-bit data has been fu lly transmitted. the wait state will be cleared when sbidbr is loaded with the next transmit data. in the external clock mode, sbidbr must be loaded with data before the next data shift operation is started. therefore, the data transfer rate varies depending on the maximum latency between when the interrupt request is generated and when sbidbr is lo aded with data in the in terrupt service program. at the beginning of transmission, the same value as in the last bit of the prev iously transmitted data is output in a period from setting sbisr to "1" to the falling edge of sck. transmission can be terminated by clearing to "0" or setting to "1" in the intsbi interrupt service program. if is cleared, re maining data is output before transmission ends. the program checks sbi0sr to determine whether transmission has come to an end. is cleared to "0" at the end of transmission. if is set to "1," the transmission is aborted immediately and is cleared to "0." in the external clock mode, must be set to "0" before the next transm it data shift operation is started. otherwise, operation will st op after dummy data is transmitted. 7 6 5 4 3 2 1 0 sbicr1 0 1 0 0 0 x x x selects the transmit mode. sbidbr x x x x x x x x writes the transmit data. sbicr1 1 0 0 0 0 x x x starts transmission. intsbi interrupt sbidbr x x x x x x x x writes the transmit data.
tmp19a64c1d tmp19a64(rev1.1)- 14-27 fig. 14.7.2.1 transmit mode example: example of programming (mips16) to te rminate transmission by (external clock) addiu r3, r0, 0x04 stest1 : lb r2, (sbisr) ; if sbisr = 1 then loop and r2, r3 bnez r2, stest1 addiu r3, r0, 0x20 stest2 : lb r2, (px) ; if sck = 0 then loop and r2, r3 beqz r2, stest2 addiu r3, r0, 0y00000111 stb r3, (sbicr1) ; 0 sbidbr intsbi interrupt request sck pin (output) so pin b a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 * is cleared a write the transmit data (a) internal clock sbidbr intsbi interrupt request sck pin (input) so pin b a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 * is cleared a write the transmit data (b) external clock
tmp19a64c1d tmp19a64(rev1.1)- 14-28 fig. 14.7.2.2 transmit data retentio n time at the end of transmission d 8-bit receive mode set the control register to the receive mode. then writing "1" to sbicr1 enables reception. data is taken into the shift regist er from the si pin, with the leas t-significant bit (lsb) first, in synchronization with the serial clock. once the shift regist er is loaded w ith the 8-bit da ta, it transfers the received data to sbidbr and the intsbi (buffe r-full) interrupt request is generated to request reading the received data. the in terrupt service program then read s the received data from sbidbr. in the internal clock mode, the serial clock will be stopped and automatically be in the wait state until the received data is read from sbidbr. in the external clock mode, shift operations are execut ed in synchronization with the external clock. the maximum data transfer rate varies, depending on the maximum latency between generating the interrupt request and re ading the received data. reception can be terminated by clearing to "0" or setting to "1" in the intsbi interrupt service program. if is cleared, r eception continues until all the bits of received data are written to sbidbr. the prog ram checks sbisr to dete rmine whether reception has come to an end. is cleared to "0" at the end of reception. af ter confirming the completion of the reception, last received data is read . if is set to "1," the reception is aborted immediately and is cleared to "0." (the received data beco mes invalid, and there is no need to read it out.) (note) the contents of sbidbr will not be retained after the transfer mode is changed. the ongoing reception must be completed by clearing to "0" and the last received data must be read before the transfer mode is changed. 7 6 5 4 3 2 1 0 sbicr1 0 1 1 1 0 x x x selects the receive mode. sbicr1 1 0 1 1 0 0 0 0 starts reception. intsbi interrupt reg. sbidbr reads the received data. bit 7 sck pin siof so pin bit 6 t sodh = min. 4/f sys /2 [s]
tmp19a64c1d tmp19a64(rev1.1)- 14-29 fig. 14.7.2.3 receive mode (example: internal clock) e 8-bit transmit/receive mode set the control register to the transfer/receive mode. then writin g the transmit data to sbidbr and setting sbicr1 to "1" enable s transmission and reception. the transmit data is output through the so pin at the falling of the serial clock, and the received data is taken in through the si pin at the rising of the serial clock, with the least-significant bit (lsb) first. on ce the shift register is loaded with the 8-bit data, it transfers the received data to sbidbr and the ints bi interrupt request is generated. the interrupt service program reads the received data from the data buffer register and writes the next transmit data. because sbidbr is shared between transmit and receive operations, the received data must be read before the next transmit data is written. in the internal clock operation, th e serial clock will be automatically in the wait state until the received data is read and the next transmit data is written. in the external clock mode, shift operations are exec uted in synchronization w ith the external serial clock. therefore, the received data must be read and the next transmit data must be written before the next shift operation is started. the maximum data tr ansfer rate for the external clock operation varies depending on the maximum latency between generati ng the interrupt request and reading the received data and writing the transmit data. at the beginning of transmission, the same value as in the last bit of the prev iously transmitted data is output in a period from setting to "1" to the falling edge of sck. transmission and reception ca n be terminated by clea ring to "0" or setting sbicr1 to "1" in the intsbi interrupt service program. if is cleared, transmission and reception continue until the received data is fully transferred to sbidbr. th e program checks sbisr to determine whether transmission and reception have come to an end. is cleared to "0" at the end of transmission and rece ption. if is set, the transmission and reception are aborted immediately and is cleared to "0." (note) the contents of sbid br will not be retained af ter the transfer mode is changed. the ongoing transmission and reception must be completed by clearing to "0" and the last received data must be read before the transfer mode is changed. sbidbr intsbi interrupt request sck pin (output) si pin b is cleared a a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 read the received data read the received data
tmp19a64c1d tmp19a64(rev1.1)- 14-30 fig. 14.7.2.4 transmit/receive mode (example: internal clock) fig. 14.7.2.5 transmit data retention time at the end of transmission/reception (in the transmit/receive mode) 7 6 5 4 3 2 1 0 sbicr1 0 1 1 0 0 x x x selects the transmit mode. sbidbr x x x x x x x x writes the transmit data. sbicr1 1 0 1 0 0 x x x starts reception/transmission. intsbi interrupt reg. sbiodbr reads the received data. sbidbr x x x x x x x x writes the transmit data. sbidbr intsbi interrupt request sck pin (output) so pin si pin is cleared c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 write the transmit data (a) read the received data (d) a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 * d b c a read the received data (c) write the transmit data (b) bit 7 of the last word transmitted sck pin siof so pin bit 6 t sodh = min. 2/f sys /2 [s]
tmp19a64c1d tmp19a64(rev1.1)- 15-1 15. analog/digital converter a 10-bit, sequential-conversion analog/digital converter (a/d converter) is built into the tmp19a64. this a/d converter is equipped with 24 analog input channels. fig. 15.1 shows the block diagram of this a/d converter. these 24 analog input channels (pins an0 through an23) are also used as input ports. (note) if it is necessary to reduce a power current by operating the tmp19a64 in idle, sleep, slow or stop mode and if either case shown below is applicable, you must first stop the a/d converter and then execute the instruction to put the tmp19a64 into standby mode: 1) the tmp19a64 must be put into id le mode when admod1 is "0." 2) the tmp19a64 must be put into sleep, slow or stop mode. interrupt request intad ain23(p97) an15(p87) an7(p77) an0(p70) comparator vrefh vrefl internal data bus multiplexer sample hold admod1 scan repeat interrupt busy end start + ? internal data bus internal data bus channel select control circuit a/d conversion result register adreg08l-7fl adreg08h-7fh d/a converter admod0 admod2 admod3 top-priority ad conversion control interval end ad conversion result register adregsp comparator comparison register top-priority ad conversion completion interrupt ad monitor function interrupt ad monitor function control busy ad start control admod4 tb0 ads hpadce adscn vref tb9 normal a/d conversion control circuit fig. 15.1 a/d converter block diagram
tmp19a64c1d tmp19a64(rev1.1)- 15-2 15.1 control register the a/d converter is controlled by a/d mode control registers (admod0, admod1, admod2, admod3 and admod4). results of a/d conversion are stored in 16 upper and lower a/d conversion result registers adreg08h/l through adreg7fh/l. results of high-p riority conversion are stored in adregsph/l. fig. 15.1.1 shows the registers related to the a/d converter. a/d mode control register 0 7 6 5 4 3 2 1 0 bit symbol eocfn adbfn itm1 itm0 repeat scan ads read/write r r r/w after reset 0 0 0 0 0 0 0 0 function normal a/d conversion completion flag 0: before or during conversion 1: completion normal a/d conversion busy flag 0: conversion stop 1: during conversion "0" is read. specify interrupt in fixed channel repeat conversion mode specify interrupt in fixed channel repeat conversion mode specify repeat mode 0: single conversion mode 1: repeat conversion mode specify scan mode 0: fixed channel mode 1: channel scan mode start a/d conversion 0: don t care 1: start conversion "0" is always read. specify a/d conversion interrupt in fixed channel repeat conversion mode fixed channel repeat conversion mode = "0," = "1" 00 generate interrupt once every single conversion 01 generate interrupt once every 4 conversions 10 generate interrupt once every 8 conversions 11 setting prohibited a dmod0 (0xffff_f314) fig. 15.1.1 registers rela ted to the a/d converter
tmp19a64c1d tmp19a64(rev1.1)- 15-3 a/d mode control register 1 7 6 5 4 3 2 1 0 bit symbol vrefon i2ad adscn adch4 adch3 adch2 adch1 adch0 read/write r/w after reset 0 0 0 0 0 0 0 0 function vref application control 0: off 1: on idle 0: stop 1: activate specify operation mode for channel scanning 0: 4ch scan 1: 8ch scan select analog input channel select analog input channel 0 fixed channel 1 4 channel scan (adscn=0) 1 8 channel scan (adscn=1) 00000 an0 an0 an0 00001 an1 an0 to an1 an0 to an1 00010 an2 an0 to an2 an0 to an2 00011 an3 an0 to an3 an0 to an3 00100 an4 an4 an0 to an4 00101 an5 an4 to an5 an0 to an5 00110 an6 an4 to an6 an0 to an6 00111 an7 an4 to an7 an0 to an7 01000 an8 an8 an8 01001 an9 an8 to an9 an8 to an9 01010 an10 an8 to an10 an8 to an10 01011 an11 an8 to an11 an8 to an11 01100 an12 an12 an8 to an12 01101 an13 an12 to an13 an8 to an13 01110 an14 an12 to an14 an8 to an14 01111 an15 an12 to an15 an8 to an15 10000 an16 an16 an16 10001 an17 an16 to an17 an16 to an17 10010 an18 an16 to an18 an16 to an18 10011 an19 an16 to an19 an16 to an19 10100 an20 an20 an16 to an20 10101 an21 an20 to an21 an16 to an21 10110 an22 an20 to an22 an16 to an22 10111 an23 an20 to an23 an16 to an23 a dmod1 (0xffff_f315) (note 1) before starting ad conversion, write "1" to the bit, wait for 3 s during which time the internal re ference voltage should stabilize, and then write "1" to the admod0 bit. (note 2) to go into standby mode upon completion of ad conversion, set to "0." fig. 15.1.2 registers rela ted to the a/d converter
tmp19a64c1d tmp19a64(rev1.1)- 15-4 a/d mode control register 2 7 6 5 4 3 2 1 0 bit symbol eocfhp adbfhp hpadce hpadch4 hpadch3 hpadch2 hpadch1 hpadch0 read/write r r/w after reset 0 0 0 0 0 0 0 0 function top-priority ad conversion completion flag 0: before or during conversion 1: upon completion top-priority ad conversion busy flag 0: during conversion halts 1: during conversion activate top-priority ad conversion 0:don?t care 1: start conversion "0" is always read. select analog input channel when activating top-priority ad conversion analog input channel when executing top-priority ad conversion 00000 an0 00001 an1 00010 an2 00011 an3 00100 an4 00101 an5 00110 an6 00111 an7 01000 an8 01001 an9 01010 an10 01011 an11 01100 an12 01101 an13 01110 an14 01111 an15 10000 an16 10001 an17 10010 an18 10011 an19 10100 an20 10101 an21 10110 an22 10111 an23 a dmod2 (0xffff_f316) fig. 15.1.3 registers rela ted to the a/d converter
tmp19a64c1d tmp19a64(rev1.1)- 15-5 a/d mode control register 3 7 6 5 4 3 2 1 0 bit symbol adobic regs3 regs2 regs1 regs0 adobsv read/write r/w r r/w r/w r/w after reset 0 0 0 0 0 0 0 0 function write "0." "0" is read. make ad monitor function interrupt setting 0: smaller than comparison regi 1: larger than comparison regi bit for selecting the ad conversion result storage regi that is to be compared with the comparison regi if the ad monitor function is enabled ad monitor function 0: disable 1: enable ad conversion result storage regi to be compared 0000 adreg08 0001 adreg19 0010 adreg2a 0011 adreg3b 0100 adreg4c 0101 adreg5d 0110 adreg6e 0111 adreg7f 1xxx adregsp a dmod3 (0xffff_f317) a/d mode control register 4 7 6 5 4 3 2 1 0 bit symbol hadhs hadhtg adhs adhtg adrst1 adrst0 read/write r/w r w w after reset 0 0 0 0 0 0 0 function hw source for activating top-priority a/d conversion 0: inttb90 1: inttb91 hw for activating top-priority a/d conversion 0: disable 1: enable hw source for activating normal a/d conversion 0: inttb00 1: inttb01 hw for activating normal a/d conversion 0: disable 1: enable ?0? is read. overwriting 10 with 01 allows adc to be software reset. all registers except the adclk register are initialized. a dmod4 (0xffff_f318) (note 1) if ad conversion is executed with the match triggers and of a 16-bit timer set to "1" by using a source for triggering h/w, a/d conversion can be activated at specified intervals by performing three steps shown below when the timer is idle: c select a source for triggering hw: , d enable h/w activation of ad conversion: , e start the timer. (note 2) do not make a high-priority ad conv ersion setting and a normal ad conversion setting simultaneously. fig. 15.1.4 registers rela ted to the a/d converter
tmp19a64c1d tmp19a64(rev1.1)- 15-6 lower a/d conversion result register 08 7 6 5 4 3 2 1 0 bit symbol adr01 adr00 ovr0 adr0rf read/write r r r r after reset 0 0 1 1 1 1 0 0 function store lower 2 bits of a/d conversion result "1" is read. over run flag 0: not generate 1: generate a/d conversion result storage flag 1: presence of conversion result upper a/d conversion result register 08 7 6 5 4 3 2 1 0 bit symbol adr09 adr08 adr07 adr06 adr05 adr04 adr03 adr02 read/write r after reset 0 0 0 0 0 0 0 0 function store upper 8 bits of a/d conversion result lower a/d conversion result register 19 7 6 5 4 3 2 1 0 bit symbol adr11 adr10 ovr1 adr1rf read/write r r r r after reset 0 0 1 1 1 1 0 0 function store lower 2 bits of a/d conversion result "1" is read. over runflag 0: not generate 1: generate a/d conversion result storage flag 1: presence of conversion result upper a/d conversion result register 19 7 6 5 4 3 2 1 0 bit symbol adr19 adr18 adr17 adr16 adr15 adr14 adr13 adr12 read/write r after reset 0 0 0 0 0 0 0 0 function store upper 8 bits of a/d conversion result 9 876543210 converted channel x value 7 6543210 7654 3 2 1 0 a dreg08h (0xffff_f301) a dreg19h (0xffff_f303) a dregxh adregx l a dreg08l (0xffff_f300) a dreg19l (0xffff_f302) fig. 15.1.5 registers rela ted to the a/d converter ? values read from bits 5 through 2 of registers adreg08l and adreg19l are always "1." ? bit 0 of registers adreg08l and adreg19l is the a/d conversi on result storage flag . this bit is set to "1" after an a/d converted value is stored. a read of a lo wer register (adregxl) clears this bit to "0." ? bit 1 of registers adreg08l and adreg19l is the over run flag . this bit is set to "1" if a conversion result is overwritten before both conversion result storage registers (adregxh and adregxl) are read. a read of a flag will clear this bit to "0." ? when reading conversion result storage registers, first read upper registers and then lower registers.
tmp19a64c1d tmp19a64(rev1.1)- 15-7 lower a/d conversion result register 2a 7 6 5 4 3 2 1 0 bit symbol adr21 adr20 ovr2 adr2rf read/write r r r r after reset 0 0 1 1 1 1 0 0 function store lower 2 bits of a/d conversion result "1" is read. over run flag 0: not generate 1: generate a/d conversion result storage flag 1: presence of conversion result upper a/d conversion result register 2a 7 6 5 4 3 2 1 0 bit symbol adr29 adr28 adr27 adr26 adr25 adr24 adr23 adr22 read/write r after reset 0 0 0 0 0 0 0 0 function store upper 8 bits of a/d conversion result lower a/d conversion result register 3b 7 6 5 4 3 2 1 0 bit symbol adr31 adr30 ovr3 adr3rf read/write r r r r after reset 0 0 1 1 1 1 0 0 function store lower 2 bits of a/d conversion result "1" is read. over run flag 0: not generate 1: generate a/d conversion result storage flag 1: presence of conversion result upper a/d conversion result register 3b 7 6 5 4 3 2 1 0 bit symbol adr39 adr38 adr37 adr36 adr35 adr34 adr33 adr32 read/write r after reset 0 0 0 0 0 0 0 0 function store upper 8 bits of a/d conversion result 9 8 7 6 5 4 3 2 1 0 converted channel x value 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 a dreg2ah (0xffff_f305) a dreg3bh (0xffff_f307) a dregxh adregxl a dreg2al (0xffff_f304) a dreg3bl (0xffff_f306) ? values read from bits 5 through 2 of registers adreg2al and adreg3bl are always "1." ? bit 0 of registers adreg2al and adreg3bl is the a/d conversion result storage flag . this bit is set to "1" after an a/d converted value is stored. a read of a lower register (adregxl) clears this bit to "0." ? bit 1 of registers adreg2al and adreg3bl is the over run flag . this bit is set to "1" if a conversion result is overwritten before both conversion result storage registers (adr egxh and adregxl) are read. a read of a flag will clear this bit to "0." ? when reading conversion result storage registers, fi rst read upper registers and then lower registers. fig. 15.1.6 registers rela ted to the a/d converter
tmp19a64c1d tmp19a64(rev1.1)- 15-8 lower a/d conversion result register 4c 7 6 5 4 3 2 1 0 bit symbol adr41 adr40 ovr4 adr4rf read/write r r r r after reset 0 0 1 1 1 1 0 0 function store lower 2 bits of a/d conversion result "1" is read. over run flag 0: not generate 1: generate a/d conversion result storage flag 1: presence of conversion result upper a/d conversion result register 4c 7 6 5 4 3 2 1 0 bit symbol adr49 adr48 adr47 adr46 adr45 adr44 adr43 adr42 read/write r after reset 0 0 0 0 0 0 0 0 function store upper 8 bits of a/d conversion result lower a/d conversion result register 5d 7 6 5 4 3 2 1 0 bit symbol adr51 adr50 ovr5 adr5rf read/write r r r r after reset 0 0 1 1 1 1 0 0 function store lower 2 bits of a/d conversion result "1" is read. over run flag 0: not generate 1: generate a/d conversion result storage flag 1: presence of conversion result upper a/d conversion result register 5d 7 6 5 4 3 2 1 0 bit symbol adr59 adr58 adr57 adr56 adr55 adr54 adr53 adr52 read/write r after reset 0 0 0 0 0 0 0 0 function store upper 8 bits of a/d conversion result 9 8 76543210 converted channel x value 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 a dreg4ch (0xffff_f309) a dreg5dh (0xffff_f30b) a dregxh adregxl a dreg5dl (0xffff_f30a) a dreg4cl (0xffff_f308) ? values read from bits 5 through 2 of registers adreg4cl and adreg5dl are always "1." ? bit 0 of registers adreg4cl and adreg5dl is the a/d conversion result storage flag . this bit is set to "1" after an a/d converted value is stored. a read of a lower register (adregxl) clears this bit to "0." ? bit 1 of registers adreg4cl and adreg5dl is the over run flag . this bit is set to "1" if a conversion result is overwritten before both conversion result storage registers (adregxh and adregxl) are read. a read of a flag will clear this bit to "0." ? when reading conversion result storage registers, first read upper registers and then lower registers. fig. 15.1.7 registers rela ted to the a/d converter
tmp19a64c1d tmp19a64(rev1.1)- 15-9 lower a/d conversion result register 6e 7 6 5 4 3 2 1 0 bit symbol adr61 adr60 ovr6 adr6rf read/write r r r r after reset 0 0 1 1 1 1 0 0 function store lower 2 bits of a/d conversion result "1" is read. over run flag 0: not generate 1: generate a/d conversion result storage flag 1: presence of conversion result upper a/d conversion result register 6e 7 6 5 4 3 2 1 0 bit symbol adr69 adr68 adr67 adr66 adr65 adr64 adr63 adr62 read/write r after reset 0 0 0 0 0 0 0 0 function store upper 8 bits of a/d conversion result lower a/d conversion result register 7f 7 6 5 4 3 2 1 0 bit symbol adr71 adr70 ovr7 adr7rf read/write r r r r after reset 0 0 1 1 1 1 0 0 function store lower 2 bits of a/d conversion result "1" is read. over runflag 0: not generate 1: generate a/d conversion result storage flag 1: presence of conversion result upper a/d conversion result register 7f 7 6 5 4 3 2 1 0 bit symbol adr79 adr78 adr77 adr76 adr75 adr74 adr73 adr72 read/write r after reset 0 0 0 0 0 0 0 0 function store upper 8 bits of a/d conversion result 9 8 76543210 converted channel x value 7 6543210 7654 3 2 1 0 a dreg6eh (0xffff_f30d) a dreg7fh (0xffff_f30f) a dregxh adregxl a dreg6el (0xffff_f30c) a dreg7fl (0xffff_f30e) ? values read from bits 5 through 2 of registers adreg6el and adreg7fl are always "1." ? bit 0 of registers adreg6el and adreg7fl is the a/d conversion result storage flag . this bit is set to "1" after an a/d converted value is stored. a read of a lower register (adregxl) clears this bit to "0." ? bit 1 of registers adreg6el and adreg7fl is the over run flag . this bit is set to "1" if a conversion result is overwritten before both conversion result storage registers (adregxh and adregxl) are read. a read of a flag will clear this bit to "0." ? when reading conversion result storage registers, first read upper registers and then lower registers. fig. 15.1.8 registers rela ted to the a/d converter
tmp19a64c1d tmp19a64(rev1.1)- 15-10 lower a/d conversion result register sp 7 6 5 4 3 2 1 0 bit symbol adrsp1 adrsp0 ovrsp adrsprf read/write r r r r after reset 0 0 1 1 1 1 0 0 function store lower 2 bits of a/d conversion result "1" is read. over run flag 0: not generate 1: generate a/d conversion result storage flag 1: presence of conversion result upper a/d conversion result register sp 7 6 5 4 3 2 1 0 bit symbol adrsp9 adrsp8 adrsp7 adrsp6 adrsp5 adrsp4 adrsp3 adrsp2 read/write r after reset 0 0 0 0 0 0 0 0 function store upper 8 bits of a/d conversion result 9 8 76543210 converted channel x value 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 a dregsph (0xffff_f311) a dregxh adregxl a dregspl (0xffff_f310) ? values read from bits 5 through 2 of register adregspl are always "1." ? bit 0 of register adregspl is the a/d conversion result storage flag . this bit is set to "1" after an a/d converted value is stored. a read of a lower register (adregxl) clears this bit to "0." ? bit 1 of register adregspl is the over run flag . this bit is set to "1" if a conversion result is overwritten before both conversion result storage registers (adregxh and adregxl) are read. a read of a flag will clear this bit to "0." ? when reading conversion result storage registers, first read upper registers and then lower registers. fig. 15.1.9 registers rela ted to the a/d converter
tmp19a64c1d tmp19a64(rev1.1)- 15-11 lower a/d conversion result comparison register 7 6 5 4 3 2 1 0 bit symbol adr21 adr20 read/write r/w r after reset 0 0 0 0 0 0 0 0 function store lower 2 bits of a/d conversion result comparison "0" is read. upper a/d conversion result comparison register 7 6 5 4 3 2 1 0 bit symbol adr29 adr28 adr27 adr26 adr25 adr24 adr23 adr22 read/write r/w after reset 0 0 0 0 0 0 0 0 function store upper 8 bits of a/d conversion result comparison a dcomregh (0xffff_f313) a dcomreg (0xffff_f312) (note) to set or change a value in this register, the ad monitor function must be disabled (admod3="0"). fig. 15.1.10 registers rela ted to the a/d converter
tmp19a64c1d tmp19a64(rev1.1)- 15-12 15.2 conversion clock z the conversion time is calculated based on the 41 conversion clock and the sample hold time. a/d conversion clock setting register 7 6 5 4 3 2 1 0 bit symbol tsh2 tsh1 tsh0 adclk2 adclk1 adclk0 read/write r/w r/w r/w r/w r r/w r/w r/w after reset 0 0 0 0 0 0 1 1 function write "0." select the a/d sample hold time 000:12 conversion clock 001:12 2 conversion clock 010: 12 3 conversion clock 011: 12 4 conversion clock 100: 12 16 conversion clock 101: 12 64 conversion clock 110: 12 256 conversion clock 111: 12 1024 conversion clock select the a/d prescaler output 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 111:reserved a dclk (0xffff_f31c) conversion clock sample hold time tconv. conversion clk*12*1 (1.78 us) 7.85 us conversion clk*12*2 (3.56 us) 9.63 us conversion clk*12*3 (5.33 us) 11.4 us conversion clk*12*4 (7.11 us) 13.2 us conversion clk*12*16 (28.4 us) 34.5 us conversion clk*12*64 (114 us) 120 us conversion clk*12*256 (455 us) 461 us 6.75 mhz conversion clk*12*1024 (1.82 ms) 1.83 ms 1 2 4 8 16 fc adclk2:0 adclk
tmp19a64c1d tmp19a64(rev1.1)- 15-13 15.3 description of operations 15.3.1 analog reference voltage the "h" level of the analog reference voltage shall be applied to the vrefh pin, and the "l" level shall be applied to the vrefl pin. by writing "0" to the ad mod1 bit, a switched-on state of vrefh- vrefl can be turned into a switched-off state. to star t ad conversion, make sure that you first write "1" to the bit, wait for 3 s during which time the internal reference voltage should stabilize, and then write "1" to the admod0 bit. 15.3.2 selecting the analog input channel how the analog input channel is selected is differ ent depending on a/d converter operation mode used. (1) normal ad conversion mode ? if the analog input channel is used in a fixed state (admod0 = "0"): one channel is selected from analog input pins ain0 through ain23 by setting admod1 to an appropriate setting. ? if the analog input channel is used in a scan state (admod0 = "1"): one scan mode is selected from 24 scan modes by setting admod1 and adscn to appropriate settings. (2) high-priority ad conversion mode one channel is selected from analog input pins ain0 through ain23 by setting admod2 to an appropriate setting. after a reset, admod0 is initialized to "0 " and admod1 is initialized to "0000." this initialization works as a trigger to select a fixed channel input through the an0 pin. the pins that are not used as analog input channels can be used as ordinary input ports. if high-priority ad conversion is activated during normal ad conversion, normal ad conversion is discontinued, high-priority ad conversion is executed and completed, and then normal ad conversion is resumed. example: a case in which repeat-scan conversion is ongoing at channels ain0 through ain3 with admod0 set to "11" and admod1 set to 00011, and high-priority ad conversion has been activated at ain15 with admod2=01111: ch0 ch1 ch2 ch15 ch2 ch3 ch0 top-priority ad has been activated conversion ch
tmp19a64c1d tmp19a64(rev1.1)- 15-14 15.3.3 starting a/d conversion two types of a/d conversion are supported: normal ad conversion and high-priority ad conversion. normal ad conversion is software activated by setting admod0 to "1." high-priority ad conversion is software activated by setting admod2 to "1." 4 operation modes are made available to normal ad conversion. in performing normal ad conversion, one of these operation modes must be selected by setting admod0<2:1> to an appropriate setting. for high-priority ad conversion, only one operation mode can be used: fixed channel single conversion mode. normal ad conversion can be activated using the hw activation source se lected by admod4, and high-priority ad conversion can be activated using the hw activation s ource selected by admod4. if this bit is "0," normal ad conversion is activated in response to inttb00 generated by the 16-bit timer 0, and high- priority ad conversion is activated in response to intt b90 generated by the 16-bit timer 9. if this bit is "1," normal ad conversion is activated in response to inttb01 generated by the 16-bit timer 0, and high- priority ad conversion is activated in response to inttb91 generated by the 16-bit timer 9. software activation is still valid even after h/w activation has been authorized. when normal a/d conversion starts, the a/d conversion busy flag (admod0) showing that a/d conversion is under way is set to "1." when high-pri ority a/d conversion starts , the a/d conversion busy flag (admod2) showing that a/d conversion is under way is set to "1." if normal a/d conversion is interrupted by high-priority a/d conversion, the value of the busy flag for normal a/d conversion before the start of high-priority a/d conversion is retained. the value of the conversion completion flag eocfn for normal a/d conversion befo re the start of high-pri ority a/d conversion can also be retained. (note) normal a/d conversion must not be activated when high-priority a/d conversion is under way. if activated when high-priority a/d conversion is under way, the high-priority a/d conversion completion flag cannot be set, and the flag for previous normal a/d conversion cannot be cleared. to reactivate normal a/d conversion, a software re set (admod4) must be performed before starting a/d conversion. the hw activation method must not be used to reactivate normal a/d conversion. if admod2 is set to "1" during normal a/d conversion, ongoing a/d conversion is discontinued and high-priority a/d conversion starts; specifically, a/d conversion (fixed channel single conversion) is executed for a channel designated by ad mod2<3:0>. after the result of this high-priority a/d conversion is stored in the storage register adregsp, normal a/d conversion is resumed. if hw activation of high-priority a/d conversion is authorized during normal a/d conversion, ongoing a/d conversion is discontinued when requirements for activation using a resource are met, and high- priority a/d conversion (fixed channel single conversion) starts for a channel designated by admod2<3:0>. after the result of this high-priority a/d conversion is stored in the storage register adregsp, normal a/d conversion is resumed.
tmp19a64c1d tmp19a64(rev1.1)- 15-15 15.3.4 a/d conversion modes and a/d conversion completion interrupts for a/d conversion, the following four operation modes are supported. for normal a/d conversion, an operation mode can be selected by setting admod0<2:1> to an appropriate setting. for high-priority a/d conversion, the fixed channel single conversion mode is automatically selected, irrespective of the admod0<2:1> setting. ? fixed channel single conversion mode ? channel scan single conversion mode ? fixed channel repeat conversion mode ? channel scan repeat conversion mode (1) normal a/d conversion an operation mode is selected with admod0< repeat, scan>. as a/d conversion starts, admod0 is set to "1." when specified a/d conversion is completed, the a/d conversion completion interrupt (intad) is generated, and admod0 showing the completion of a/d conversion is set to "1." if ="0," returns to "0" concurrently with the setting of eocf. if is set to "1," remains at "1" and a/d conversion continues. c fixed channel single conversion mode if admod0 is set to "00," a/ d conversion is performed in the fixed channel single conversion mode. in this mode, a/d conversion is performed once for one channel selected. after a/d conversion is completed, admod0 is set to "1," admod0< adbf> is cleared to "0," and the interrupt request intad is generated. is cleared to "0" upon read. d channel scan single conversion mode if admod0 is set to "01," a/d conversion is performed in the channel scan single conversion mode. in this mode, a/d conversion is performed once for each scan channel selected. after a/d scan conversion is completed, admod0 is se t to "1," admod0 is cleared to "0," and the interrupt request intad is generate d. is cleared to "0" upon read. e fixed channel repeat conversion mode if admod0 is set to "10," a/d conversion is performed in fixed channel repeat conversion mode. in this mode, a/d conversion is performed repeatedly for one channel selected. after a/d conversion is completed, admod is se t to "1." admod0 is not cleared to "0." it remains at "1." the timing with which the interrupt request intad is generated can be selected by setting admod0 to an appropriate setting. is set with the same timing as this interrupt intad is generated. is cleared to "0" upon read. with set to "00," an interrupt request is generated each time one a/d conversion is completed. in this case, the conversion results ar e always stored in the storage register adreg08. after the conversion result is stored, eocf changes to "1." with set to "01," an interrupt request is generated each time four a/d conversion are completed. in this case, the conversion results are sequentially stored in storage registers adreg08 through adreg3b. after the conversion results are stored in adreg3b, is set to "1," and the storage of subsequent conver sion results starts from adreg08. is cleared to "0" upon read.
tmp19a64c1d tmp19a64(rev1.1)- 15-16 with set to "10," an interrupt request is generated each time eight a/d conversions are completed. in this case, the conversion results are sequentially stored in storage registers adreg08 through adreg7f. after the conversion results are stored in adreg7f, is set to "1," and the storage of subsequent conversion results starts from adreg08. is cleared to "0" upon read. f channel scan repeat conversion mode if admod0 is set to "11," a/d conversion is performed in the channel scan repeat conversion mode. in this mode, a/d conversion is performed repeatedly for a scan channel selected. each time one a/d scan conversion is completed, admod0 is set to "1," and the interrupt request intad is generated. admod0 is not clear ed to "0." it remains at "1." is cleared to "0" upon read. to stop the a/d conversion operation in the repeat conversion mode (modes described in e and f above), write "0" to admod0 . when ongoing a/d conversion is completed, the repeat conversion mode terminates, and admod0 is set to "0." (2) high-priority a/d conversion high-priority a/d conversion is performed only in fixed channel single conversion mode. the admod0 setting has no relevance to the high-priority a/d conversion operations or preparations. as ac tivation requirements are met, a/ d conversion is performed only once for a channel designated by admod2. after the a/d conversion is completed, the high-priority a/d conversi on completion interrupt is generated, admod2 is set to "1," and re turns to "0." the eocfhp flag is cleared upon read.
tmp19a64c1d tmp19a64(rev1.1)- 15-17 relationships between a/d conversion modes, in terrupt generation timings and flag operations admod0 conversion mode interrupt generation timing eocf setting timing (see note) adbf (after the interrupt is generated) itm1:0 repeat scan fixed channel single conversion after conversion is completed after conversion is completed 0 ? 0 0 each time one conversion is completed after one conversion is completed 1 00 each time four conversions are completed after four conversions are completed 1 01 fixed channel repeat conversion each time eight conversions are completed after eight conversions are completed 1 10 1 0 channel scan single conversion after scan conversion is completed after scan conversion is completed 1 ? 0 1 channel scan repeat conversion each time one scan conversion is completed after one scan conversion is completed 1 ? 1 1 (note) eocf is cleared upon read. fig. 15.3.4.1 relationships between a/d conversi on modes, interrupt generation timings and flag operations
tmp19a64c1d tmp19a64(rev1.1)- 15-18 15.3.5 high-priority conversion mode by interrupting ongoing normal a/d conversion, high-priority a/d conversion can be performed. high- priority a/d conversion can be software activat ed by setting admod2 to "1" or it can be activated using the hw resource by setting admod4<7:6> to an appropriate setting. if high-priority a/d conversion has been activated during normal a/d conversion, ongoing normal a/d conversion is interrupted, and single conversion is performed for a channel designated by admod2<3:0>. the result of single conversion is stored in adregsp, and the high-priority a/d conversion interrupt is generated. after high-priority a/d conversion is completed, normal a/d conversion is resumed; the status of normal a/d conversion immediately before being interrupted is maintained. high-priority a/d conversion activated while high-priority a/d conversion is under way is ignored. for example, if channel repeat conversion is activated for channels an0 through an8 and if is set to "1" during an3 conversion, an3 conversion is suspended, and conversion is performed for a channel designated by . after the result of conversion is stored in adregsp, channel repeat conversion is resumed, starting from an3. 15.3.6 a/d monitor function if admod3 is set to "1," the a/d monitor f unction is enabled. if the value of the conversion result storage register specified by regs<3:0> become s larger or smaller ("larger" or "smaller" to be designated by adobic) than the value of a comparison register, the a/d monitor function interrupt is generated. this comparison operation is performe d each time a result is stored in a corresponding conversion result storage register, and the interrupt is generated if the conditions are met. because storage registers assigned to perform the a/d monitor function are usually not read by software, overrun flag is always set and the conversion result storage flag is also set. to use the a/d monitor function, therefore, a flag of a corresponding conversion result storage register must not be used. 15.3.7 a/d conversion time by setting adclk to an appropriate setting, one a/d conversion clock can be selected for fc, fc/2, fc/4, fc/8 and fc/16 (ad pres caler outputs). to achieve the guara nteed accuracy, the a/d conversion clock must be 6.75 mhz or less, that is, the a/d conversion time must be 7.85 s or longer. 15.3.8 storing and reading a/d conversion results a/d conversion results are stored in upper and lowe r a/d conversion result registers for normal a/d conversion (adreg08h/l through adrg7fh/l). in fixed channel repeat conversion mode, a/d conversion results are sequentially stored in adreg08h/l through adreg7fh/l. if is so set as to generate the interrup t each time one a/d conversion is completed, conversion results are stored only in adreg 08h/l. if is so set as to generate the interrupt each time four a/d conversions are complete d, conversion results are sequentially stored in adreg08h/l through adreg3bh/l. table 15.3.8.1 shows analog input channels and related a/d conversion result registers.
tmp19a64c1d tmp19a64(rev1.1)- 15-19 table 15.3.8.1 analog input channels and re lated a/d conversion result registers a/d conversion result register analog input channel conversion modes other than shown to the right fixed channel repeat conversion mode (every one conversion) fixed channel repeat conversion mode (every four conversions) fixed channel repeat conversion mode (every eight conversions) an0 adreg08h/l an1 adreg19h/l an2 adreg2ah/l an3 adreg3bh/l an4 adreg4ch/l an5 adreg5dh/l an6 adreg6eh/l an7 adreg7fh/l an8 adreg08h/l an9 adreg19h/l an10 adreg2ah/l an11 adreg3bh/l an12 adreg4ch/l an13 adreg5dh/l an14 adreg6eh/l an15 adreg7fh/l an16 adreg08h/l an17 adreg19h/l an18 adreg2ah/l an19 adreg3bh/l an20 adreg4ch/l an21 adreg5dh/l an22 adreg6eh/l an23 adreg7fh/l adreg08h/l fixed a dreg08h/l a dreg3bh/l a dreg08h/l a dreg7fh/l 15.3.9 data polling to process a/d conversion results without using inte rrupts, admod0 must be polled. if this flag is set, conversion results are stored in a specified a/ d conversion result register. after confirming that this flag is set, read that conversion result storage register. in reading the register, make sure that you first read upper bits and then lower bits to detect an overrun. if ovrn is "0" and adrnrf is "1" in lower bits, a correct conversion result has been obtained.
tmp19a64c1d 16. watchdog timer (runaway detection timer) the tmp19a64 has a built-in watchdog timer for detecting runaways. the watchdog timer (wdt) is for detecting malfunctions (runaways) of the cpu caused by noises or other disturbances and remedying them to return the cpu to normal operation. if the timer detects a runaway, it generates a non-maskable interrupt to notify the cpu. by connecting the output of the watchdog timer to a reset pin (inside the chip), it is possible to force the watchdog timer to reset itself. 16.1 configuration fig. 16.1 shows the block diagram of the watchdog timer. internal reset wdmod wdmod reset watchdog timer control register wdcr q r s binary counter (22 stages) internal reset wdmod interrupt request intwdt f sys /2 selector write b1h write 4eh 2 22 /fs y s 2 20 /fs y s 2 18 /fs y s 2 16 /fs y s reset control reset pin internal data bus fig. 16.1 block diagram of the watchdog timer tmp19a64(rev1.1)- 16-1
tmp19a64c1d 16.2 watchdog timer interrupt the watchdog timer consists of the binary counters th at are arranged in 22 stages and work using the f sys/2 system clock as an input clock. the outputs produced by these binary counters are 2 15 , 2 17 , 2 19 and 2 21 . by selecting one of these outputs with wdmod , a watchdog timer interrupt can be generated when an overflow occurs, as shown in fig. 16.2.1. because the watchdog timer interrupt is a non-maskable interrupt f actor, nmiflg at the intc performs a task of identifying it. 0 wdt interrupt wdt clear (software) write of a clear code overflow n wdt counter fig. 16.2.1 normal mode when an overflow occurs, resetting the chip itself is an opti on to choose. if the chip is reset, a reset is effected for a 32-state time, as shown in fig. 16.2.2. if this reset is effected, the clock f sys that the clock gear generates by dividing the clock f c of the high-speed oscillator by 8 is used as an input clock f sys/2 . overflow wdt counter n wdt interrupt internal reset 32-state (9.48 s @ f c = 54 mhz, f sys = 6.75 mhz, f sys/2 = 3.375 mhz) fig. 16.2.2 reset mode (note 1) when the watchdog timer functions to effect a reset, sampling of the status of the plloff pin still continues. therefore, use the p lloff pin at the level fixed to "h." (note 2) if the watchdog timer is operated when the high-frequency oscillator is idle, the system reset operation initiated by the watchdog timer becomes erratic due to the unstable oscillation of the high-frequency oscillator. therefore, do not operate the watchdog timer when the high-frequency oscillator is idle. tmp19a64(rev1.1)- 16-2
tmp19a64c1d 16.3 control registers the watchdog timer (wdt) is controlled by two control registers wdmod and wdcr. 16.3.1 watchdog timer mode register (wdmod) c specifying the detection time of the watchdog timer this is a 2-bit register for specifying the watc hdog timer interrupt time for runaway detection. when a reset is effected, this register is initialized to wdmod = "00." fig. 16.3.1.1 shows the detection time of the watchdog timer. d enabling/disabling the watchdog timer when reset, wdmod is initialized to "1" and the watchdog timer is enabled. to disable the watchdog timer, this bit must be set to "0" and, at the same time, the disable code (b1h) must be written to the wdcr register. this dual setting is intended to minimize the probability that the watchdog timer may inadvertently be disabled if a runaway occurs. to change the status of the watchdog timer from "d isable" to "enable," set the bit to "1." e watchdog timer out reset connection this register is used to make a non-maskable interrupt (intwdt) setting associated with the detection of a runaway or to make a connection setting after an internal reset. after a reset, wdmod is initialized to "0," and a non-m askable interrupt setting is established. for information on the status of non-maskable inte rrupts, refer to the nmiflg register which is described in chapter 6 "interrupts." tmp19a64(rev1.1)- 16-3
tmp19a64c1d 7 6 5 4 3 2 1 0 bit symbol wdte wdtp1 wdtp0 i2wdt rescr ? read/write r/w r/w r r r/w r/w after reset 1 0 0 0 0 0 0 0 function wdt control 0: disable 1: enable selects wdt detection time 00: 2 16 /f sys 01: 2 18 /f sys 10: 2 20 /f sys 11: 2 22 /f sys i d l e 0: stop 1: start selects internal reset 0: connects nmi 1: connects internal reset write "0." wdmod (0xffff_f090) watchdog timer out control 0 nmi interrupt 1 connects wdt out to internal reset detection time of watchdog timer wdmod syscr1 clock gear value 00 01 10 11 000 (fc) 1.2 ms 4.9 ms 19.4 ms 77.7 ms 100 (fc/2) 2.4 ms 9.7 ms 38.8 ms 155.3 ms 110 (fc/4) 4.9 ms 19.4 ms 77.7 ms 310.7 ms 111 (fc/8) 9.7 ms 38.8 ms 155.3 ms 621.4 ms 0 disable 1 enable detection time of watchdog timer @ fc = 54 mhz enable/disable control of the watchdog timer fig. 16.3.1.1 watchdog timer mode register tmp19a64(rev1.1)- 16-4
tmp19a64c1d 16.3.2 watchdog timer control register (wdcr) this is a register for disabling the watchdog timer function and controlling the clearing function of the binary counter. ? disabling control by writing the disable code (b1h) to this wdcr register after setting wdmod to "0," the watchdog timer can be disabled. wdmod 0 ? ? ? ? ? ? ? clears wdte to "0." wdcr 1 0 1 1 0 0 0 1 writes the disable code (b1h). ? enabling control set wdmod to "1." ? watchdog timer clearing control writing the clear code (4eh) to the wdcr register clears the binary counter and allows it to resume counting. wdcr 0 1 0 0 1 1 1 0 writes the clear code (4eh). (note) writing the disable code (bih) clears the binary counter. 7 6 5 4 3 2 1 0 bit symbol ? read/write w after reset ? function b1h : wdt disable code 4eh : wdt clear code others: disabled this is a write-only register. if each bit is read, "0" is returned. wdcr (0xffff_f091) disable & clear of wdt b1h disable code 4eh clear code others ? fig. 16.3.2.1 watchdog timer control register tmp19a64(rev1.1)- 16-5
tmp19a64c1d 16.4 operation description the watchdog timer generates the intwd interrupt after a lapse of the detection time specified by the wdmod register. before generating the intw d interrupt, the binary counter for the watchdog timer must be cleared to "0" using software (instructi on). if the cpu malfunctions (runs away) due to noise or other disturbances and cannot execute the instruction to clear the binary counter, the binary counter overflows and the intwd interrupt is generated. the cpu is able to recognize the occurrence of a malfunction (runaway) by identifying the intwd interrupt and to restore the faulty condition to normal by using a malfunction (runaway) countermeasure program. additionally, it is possible to resolve the problem of a malfunction (runaway) of the cpu by connecting the watchdog timer out pin to reset pins of peripheral devices. the watchdog timer begins operation im mediately after a reset is cleared. in stop mode, the watchdog timer is reset and in an idle state. when the bus is open ( busak = "l"), it continues counting. in idle mode, its operation de pends on the wdmod setting. before putting it in idle mode, wdmod must be set to an appropriate setting, as required. examples: c to clear the binary counter 7 6 5 4 3 2 1 0 wdcr 0 1 0 0 1 1 1 0 writes the clear code (4eh) d to set the detection time of the watchdog timer to 2 18 /f sys 7 6 5 4 3 2 1 0 wdmod 1 0 1 ? ? ? ? ? e to disable the watchdog timer 7 6 5 4 3 2 1 0 wdmod 0 ? ? ? ? ? ? ? clears wdte to "0" wdcr 1 0 1 1 0 0 0 1 writes the disable code (b1h) note: if the watchdog timer is operated when the high-frequency oscillator is idle, the system reset operation initiated by the watchdog timer becomes erratic due to the unstable oscillation of the hi gh-frequency oscillator. therefore, do not operate the watchdog timer when the high-frequency oscillator is idle. tmp19a64(rev1.1)- 16-6
tmp19a64c1d 17. backup module (clock timer, backup ram) 17.1 features the tmp19a64 has a backup module (backup mode) with a built-in timer dedicated to clock operations and a built-in backup ram. using this backup module, th e tmp19a64 can operate in low-power-consumption operation modes. specifically, power to all blocks (cpu, peripheral i/os, etc.) except the backup module is disconnected; because only the backup module is supplied with power, it is possible to reduce the amount of consumption current greatly. 17.2 block diagram fig. 17.2 shows the block diagram of the backup module. low-speed oscillation circuit 512byte b-up ram clock timer other blocks cpu back-up module backup i/f tx19a64 dvcc reset breset bupmd bvcc xt1 intrtc fig. 17.2 block diagram of the backup module tmp19a64(rev1.1)- 17-1
tmp19a64c1d precautions for the use of the backup module: z low-speed oscillation starts when the backup module (bvcc) is powered on. the software start or stop of low-speed oscillation is not permitted. z to put the tmp19a64 in backup mode or normal operation mode, necessary settings must be made. z when the backup module is operating in slow mode, access to the backup ram is prohibited. z the functions that can be initialized with breset are as follows: clock timer: initialize backup ram: undefined backup module reset flag: initialize registers in the backup module (rtcflg, rtccr, rtcreg) low-speed oscillator: continued oscillation z if the backup module and the low-frequency oscillato r are not used, the following settings must be made: power supply level: bvcc, breset gnd level: xt1, bupmd 17.3 backup mode a backup mode is provided as a system operation mode. in backup mode, the power to all blocks except the backup module is disconnected so that the tmp19a64 can operate with low power consumption. fig. 17.3 is the state transition diagram showing a transition to the backup mode. slow/sleep mode normal mode a ll blocks are powered on during the full- power operation. some blocks are powered on during the low-speed operation. backup mode during the low-speed operation, only the backup power supply is powered on, only the clock timer is operating, and the ram data is retained. dvcc on reset all blocks other than bvcc are shut down. bupmd input fig. 17.3 block diagram of the backup module tmp19a64(rev1.1)- 17-2
tmp19a64c1d 17.4 backup mode operation 17.4.1 transition to backup mode to put the tmp19a64 into backup mode, first set the backup mode trigger pin (bupmd) to "0," and then cut off the main power supply (dvcc3, dvcc15). when performing these two steps, caution must be used because there is the possibility that data is bein g written to the backup ram. therefore, steps must be performed according to the sequence shown below. additionally, to reco ver from backup mode, the power must be turned on and signals must be processed according to the sequence shown below. c dvcc15 dvcc3 (internal power supply) e d f backup mode period reset bupmd z to recover from backup mode, steps c , d and e must be performed in this order. z if data is being written to the b ackup ram in the backup module, th e period (4) must be more than 50 clocks (1 sec (@54 mhz)) in orde r to guarantee the integrity of data. tmp19a64(rev1.1)- 17-3
tmp19a64c1d 17.4.2 power-on (recovery from backup mode) example: if the dvcc15 power and the bvcc power are activated with different timings dvcc3 (internal power supply) z t1: as bvcc stabilizes, breset is maintained at "l" for more than 2 ms*. (* this time length differs depending on the characteristics of the oscillator.) t2 dvcc15 (internal power supply) reset (main reset) bvcc (power supply for the backup module) breset (backup module reset) t1 t3 bupmd (backup mode signal) z t2: bupmd is set to "h" after a lapse of the warming-up time for the high-speed oscillator. z t3: reset is cleared after the level of bupm d changes to "h." (the backup module is initialized according to the initial routine.) even if the instruction to move to stop mode has been executed, low-speed oscillation continues as long as bvcc (power supply for the backup module) is supplying power. therefore, after the instruction to move to stop mode is executed, bvcc must be shut down. to recover from stop mode, first start bvcc, breset and bupmd in the same sequence as they are powered on, and then clear stop mode. tmp19a64(rev1.1)- 17-4
tmp19a64c1d 17.5 backup ram 17.5.1 features the backup module has a built-in backup ram (512 by tes) to be used when the tmp19a64 operates in low-power-consumption operation mode. this ram holds data when the tmp19a64 is operating in backup mode. the data held in the ram rema ins intact even if a reset is executed. z backup ram area (512 bytes): 0xffff_e800 through 0xffff_e9ff z data in the backup ram area is retained wh en the tmp19a64 is operating in backup mode. z the data held in the backup ram area is re tained even if a reset (/reset) is executed. z the /breset pin is used to initialize (undefined value) the backup ram area. note: concerning the access to the backup ram area for a read or write, a time length equal to 10 system clocks is required to process one such access. 17.6 clock timer 17.6.1 features the backup module has a built-in clock timer to be used when the tmp19a64 operates in low-power consumption operation mode. this clock timer using 32.768 khz as a low clock frequency can generate interrupts at time intervals of 0.125s, 0.250s, 0.500s and 1.000s so that the tmp19a64 is able to use the clock function when operating in low-power-consumption operation modes. this clock timer can be operated in all operation modes of low-frequency oscillation. the interrupt generated by the clock timer allows the tmp19a64 to recover from standby mode (except stop mode). to use the clock timer interrupt (intrtc), the imcgd re gister in the cg must be set to an appropriate setting. fig. 17.6.1 shows the block diagram of the clock timer. 15-stage binary counter selector 2 15 run& clear 2 14 2 13 2 12 fs (32.768 khz) 32-bit cumulative register rtcreg rtcflg rtccr breset clear interrupt request intrtc fig. 17.6.1 block diagra m of the clock timer tmp19a64(rev1.1)- 17-5
tmp19a64c1d 17.6.2 registers the clock timer is controlled by the clock timer cont rol register (rtccr), backup mode flag register (rtcflg), and clock timer count cumulative register (rtcreg). these registers are the 32-bit registers that can be initialized by /breset. fig. 17.6.2.1 shows the clock timer control register. (fs = 32.768 khz) 31 30 29 28 27 26 25 24 bit symbol read/write r after breset 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol read/write r after breset 0 0 0 0 0 0 0 0 function 15 14 13 12 11 10 9 8 bit symbol read/write r after breset 0 0 0 0 0 0 0 0 function 7 6 5 4 3 2 1 0 bit symbol rtcrclr rtcsel1 rtcsel0 rtcrun read/write r/w r/w r w r/w r/w after breset 0 0 0 0 0 0 0 0 function write "0." write "0." clear cumulative register 0: clear 1: don?t care interrupt generation cycle 00: 2 15 /fs (1.000 s) 01: 2 14 /fs (0.500 s) 10: 2 13 /fs (0.250 s) 11: 2 12 /fs (0.125 s) binary counter 0: stop & clear 1: count rtccr (0xffff_e704) fig. 17.6.2.1 clock timer control register (note) to access this register, 32-bit access is required. (note) values read from the registers are undefined until /breset is activated. (note) values read from rtccr are always "1." (note) before changing the rtccr setting, make sure that rtccr is "0" and that the rtc interrupt is disabled. tmp19a64(rev1.1)- 17-6
tmp19a64c1d the backup mode flag register rtcflg is a 32-bit register that has the bit for monitoring the activation of /breset and can be initialized by / breset. by writing "1" to the bit after /breset when starting the backup module, this regist er can be used as a /breset activation monitor. fig. 17.6.2.2 shows the clock timer control register. 31 30 29 28 27 26 25 24 bit symbol read/write r after breset 0 0 0 0 0 0 0 0 function see note 23 22 21 20 19 18 17 16 bit symbol read/write r after breset 0 0 0 0 0 0 0 0 function see note 15 14 13 12 11 10 9 8 bit symbol read/write r after breset 0 0 0 0 0 0 0 0 function see note 7 6 5 4 3 2 1 0 bit symbol bupflg read/write r r/w after breset 0 0 0 0 0 0 0 0 function see note breset monitor flag 0: after breset see notes rtcflg (0xffff_e700) fig. 17.6.2.2 backup mode flag register (note) values read from this register ar e undefined until /breset is activated. (note) for this register, 32-bit access is required. (note) only "1" can be written to the bit. (note) after /breset, the bit changes to "0." therefore, this register can be used as a /breset activation monito r by writing "1" after /breset when starting the backup module. tmp19a64(rev1.1)- 17-7
tmp19a64c1d the clock timer is provided with a clock count cumulative register (rtcreg) for counting the number of times interrupts are generated. if 1.0s is selected as an interrupt genera tion cycle, a maximum of 4294967296 seconds can be retained (136 years, 70 days, 6 hours, 28 minutes, and 16 seconds). clock count cumulative register 31 30 29 28 27 26 25 24 bit symbol rui31 rui30 rui29 rui28 rui27 rui26 rui25 rui24 read/write r/w after reset 0 0 0 0 0 0 0 0 function accumulate count value 23 22 21 20 19 18 17 16 bit symbol rui23 rui22 rui21 rui20 rui19 rui18 rui17 rui16 read/write r/w after reset 0 0 0 0 0 0 0 0 function accumulate count value 15 14 13 12 11 10 9 8 bit symbol rui15 rui14 rui13 rui12 rui11 rui10 rui9 rui8 read/write r/w after reset 0 0 0 0 0 0 0 0 function accumulate count value 7 6 5 4 3 2 1 0 bit symbol rui7 rui6 rui5 rui4 rui3 rui2 rui1 rui0 read/write r/w after reset 0 0 0 0 0 0 0 0 function accumulate count value rtcreg (0xffff_e708) fig. 17.6.2.3 clock count cumulative register (note) values read from this register ar e undefined until /breset is activated. (note) to access this register, 32-bit access is required. (note) a write to this cumulative register clears the prescaler. (note) interrupts must be disabled during a read. tmp19a64(rev1.1)- 17-8
tmp19a64c1d example of the clock timer interrupt setting: initialization 7 6 5 4 3 2 1 0 imcd 0 0 1 0 0 0 0 0 disables the interrupt intrtc sets the bit <23:16> of a 32-bit register rtccr 0 0 0 0 x x x 0 stops the rtc timer count sets the bit <7:0> of a 32-bit register imcgd 0 0 1 1 0 0 0 1 sets the bit <15:8> of a 32-bit register eicrcg 0 0 0 0 1 1 0 1 clears the interrupt request for the cg block set the bit <7:0> of a 32-bit register intclr 0 1 1 1 1 0 0 0 clears the interrupt request for the intc block sets the bit <8:0> of a 32-bit register rtccr 0 0 0 0 1 x x 1 starts the timer count sets the bit <7:0> of a 32-bit register imcd 0 0 1 0 0 x x x sets the interrupt level set the bit <23:16> of a 32-bit register intrtc interrupt 7 6 5 4 3 2 1 0 eicrcg 0 0 0 0 1 1 0 1 clears the interrupt request for the cg block sets the bit <7:0> of a 32-bit register intclr 0 1 1 1 1 0 0 0 clears the interrupt request for the intc block sets the bit <8:0> of a 32-bit register processing interruption finished (note 1) x means "don't care." (note 2) to disable the interrupt generated in standby mode, imcd must be first set and then imcgd. tmp19a64(rev1.1)- 17-9
tmp19a64c1d 18. key-on wakeup 18.1 outline the tmp19a64 has 8 key inputs, key0 to key7, which can be used for releasing the stop/sleep mode or for external interrupts. note that interrupt processing is executed with one interrupt factor for the 8 inputs. each key input can be configured to be used or not, by programming (kwupstn). ? ? ? ? the active state of each input can be configured to the rising edge, the falling edge, the high level or the low level, by programming (kwupstn). an interrupt request is cleared by reading the key interrupt state register kwupst in the interrupt processing. the key input pins have pull-up functions, which can be enabled or disabled by programming the key pull-up control register kuppup. 18.2 key-on wakeup operation the tmp19a64 has 8 key input pins, key0 to key7. program the imcgc0 register in the cg to determine whether to use the key inputs for releas ing the stop/sleep mode or for normal interrupts. setting to "1" causes all the key inputs, key0 to key7, to be used for interrupts for releasing the stop/sleep mode. program kwupstn to enab le or disable interrupt inputs for each key input pin. also, program kwupstn to define the active state of each key input pin to be used. detection of key inputs is carried out in the kwup bl ock, and the detection results are notified to the imcgd register in the cg as the active high level. therefor e, program imcgd to "01" to determine the detection level to the high level. the results of detec tion in the cg are also notified to the interrupt controller intc as the active high level. theref ore, program the intc to "01" to define the corresponding interrupt as the high level. setting imcgd to 0 (default) configures all the input pins, key0 to key7 to the normal interrupts. in this case, you don?t have to make settings at the cg, but just specify the intc detection level to the high level. program kwupstn in the same way to enable or disable each key input and define their active states. reading kwupst during interrupt pro cessing clears the generated key interrupt requests. (note) if two or more key inputs are generated, the interrupt requests, which have been generated before the sequence of clearing the interrupt requests carried out in the interrupt processing routine that corresponds to the first key input, will be cleared at the same time. key interrupts are generated again for the interrupt requests that are generated after the said sequence of clearing the interrupt requests. 18.3 pull-up function each key input has the pull-up function. pull-up can be enabled for each bit of key inputs key0 to key7 by setting kuppup to "1." the pull-up function does not work for the key inputs that are disabled at kwupstn, independently of the kuppup setting. tmp19a64(rev1.1)- 18-1
tmp19a64c1d cautions on use of key inputs with pull-up enabled a) when you make the first setting after turning the power on 1) set kuppup ( ="1"). 2) set kwupstn to "1" for the keyn input to be used. 3) wait until the pull-up operation is completed. 4) set kwupstn to define the active state of the keyn input to be used. 5) clear interrupt requests by reading kwupst. 6) set cg and the intc. (refer to chapter 6, "interrupt settings" for the details of setting methods.) b) to change the active state of a key input during operation 1) disable key interrupts by setting imc3 to "000" at the intc. 2) change the active state by setting kwupstn for the keyn input to be changed. 3) clear interrupt requests by reading kwupst. 4) enable the key interrupt at the intc. (set imc3 to a desired level.) c) to enable a key input during operation 1) disable key interrupts by setting imc3 to "000" at the intc. 2) set kwupstn to "1" for the key input to be used. 3) wait until the pull-up operation is completed. 4) define the active state of the key input to be used at the corresponding kwupstn. 5) clear interrupt requests by reading kwupst. 6) enable key interrupts at the intc. (set imc3< ild2:d0> to a desired level.) cautions on use of key inputs with pull-up disabled a) when you make the first setting after turning the power on 1) set kuppup ( ="0") 2) set kwupstn to define the active state of the keyn input to be used. 3) clear interrupt requests by reading kwupst. 4) set kwupstn to "1" for the keyn input to be used. 5) set cg and the intc. (refer to chapter 6, "interrupt settings" for the details of setting methods.) b) to change the active state of a key input during operation 1) disable key interrupts by setting imc3 to "000" at the intc. 2) change the active state by setting kwupstn for the key input to be changed. 3) clear interrupt requests by reading kwupst. 4) enable key interrupts at the intc. (set imc3< ild2:d0> to a desired level.) c) to enable a key input during operation 1) disable key interrupts by setting imc3 to "000" at the intc. 2) define the active state by setting kwupstn for the key input to be used. 3) clear interrupt requests by reading kwupst. 4) set kwupstn to "1" for the key input to be used. 5) enable key interrupts at the intc. (set imc3 to a desired level.) tmp19a64(rev1.1)- 18-2
tmp19a64c1d key pull-up control register: kuppup 7 6 5 4 3 2 1 0 bit symbol keypup7 keypup6 keypup5 keypup4 keypup3 keypup2 keypup1 keypup0 read/write r/w after reset 0 0 0 0 0 0 0 0 function 0: pull-up disabled 1: pull-up enabled 0: pull-up disabled 1: pull-up enabled 0: pull-up disabled 1: pull-up enabled 0: pull-up disabled 1: pull-up enabled 0: pull-up disabled 1: pull-up enabled 0: pull-up disabled 1: pull-up enabled 0: pull-up disabled 1: pull-up enabled 0: pull-up disabled 1: pull-up enabled kuppup (0xffff_f371) 18.4 key input detection 1) pull-up disabled/enabled the active state of each keyn input can be defined to the high or low level or to the rising and/or falling edges by setting kwupstn. the act ive states of keyn i nputs are continuously detected. tmp19a64(rev1.1)- 18-3
tmp19a64c1d 7 6 5 4 3 2 1 0 kwupst0 bit symbol key01 key00 key0en (0xffff_f360) read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function define the key0 active state 00: "l" level 01: "h" level 10: falling edge 11: rising edge k e y 0 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst1 bit symbol key11 key10 key1en (0xffff_f361) read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function define the key1 active state 00: "l" level 01: "h" level 10: falling edge 11: rising edge k e y 1 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst2 bit symbol key21 key20 key2en (0xffff_f362) read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function define the key2 active state 00: "l" level 01: "h" level 10: falling edge 11: rising edge k e y 2 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst3 bit symbol key31 key30 key3en (0xffff_f363) read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function define the key3 active state 00: "l" level 01: "h" level 10: falling edge 11: rising edge k e y 3 interrupt input 0: disable 1: enable tmp19a64(rev1.1)- 18-4
tmp19a64c1d 7 6 5 4 3 2 1 0 kwupst4 bit symbol key41 key40 key4en (0xffff_f364) read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function define the key4 active state 00: "l" level 01: "h" level 10: falling edge 11: rising edge k e y 4 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst5 bit symbol key51 key50 key5en (0xffff_f365) read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function define the key5 active state 00: "l" level 01: "h" level 10: falling edge 11: rising edge k e y 5 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst6 bit symbol key61 key60 key6en (0xffff_f366) read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function define the key6 active state 00: "l" level 01: "h" level 10: falling edge 11: rising edge k e y 6 interrupt input 0: disable 1: enable 7 6 5 4 3 2 1 0 kwupst7 bit symbol key71 key70 key7en (0xffff_f367) read/write r r/w r r/w after reset 0 0 1 0 0 0 0 0 function define the key7 active state 00: "l" level 01: "h" level 10: falling edge 11: rising edge k e y 7 interrupt input 0: disable 1: enable tmp19a64(rev1.1)- 18-5
tmp19a64c1d 18.5 detection of key input inte rrupts and clearance of requests when keynen is set to 1 and an active signal is inpu t to keyn, the keyintn channel that corresponds to kwupst is set to "1," indicating that an interrupt is generated. the kwupst is the read-only register. reading this register clears the correspon ding bit that has been set to "1." if the active state is set to the high or low level, the co rresponding bit of the kwupst register remains "1" after it is read, unless the exte rnal input is withdrawn. key interrupt state register: kwupst 7 6 5 4 3 2 1 0 kwupst bit symbol keyint7 keyint6 keyin t5 keyint4 keyint3 keyint2 keyint1 keyint0 (0xffff_f370) read/write r after reset 0 0 0 0 0 0 0 0 function key7 interrupt state 0: no interrupt generated 1: interrupt generated key6 interrupt state 0: no interrupt generated 1: interrupt generated key5 interrupt state 0: no interrupt generated 1: interrupt generated key4 interrupt state 0: no interrupt generated 1: interrupt generated key3 interrupt state 0: no interrupt generated 1: interrupt generated key2 interrupt state 0: no interrupt generated 1: interrupt generated key1 interrupt state 0: no interrupt generated 1: interrupt generated key0 interrupt state 0: no interrupt generated 1: interrupt generated tmp19a64(rev1.1)- 18-6
tmp19a64c1d 19. rom correction function this chapter describes the rom correction function built into the tmp19a64. 19.1 features using this function, eight pieces of one-word data or four pieces of eight-word data can be replaced. ? ? ? if an address (lower 5 or 2 bits are "don't care" bits) written to the address register matches an address generated by the pc or dmac, rom data is replaced by data generated by the rom correction data register which is established in a ram area assigned to the above address register. rom correction is automatically authorized by writing an address to each address register. 19.2 description of operations by setting in the address register addregn a physical ad dress (including a projection area) of the rom area to be corrected, rom data can be replaced by data generated by a data register in a ram area assigned to addregn. the rom correction function is automatically en abled when an address is set in addregn, and it cannot be disabled. after a reset, the rom correction function is disabled. therefore, to execute rom correction with the initial setting after a reset is cleared, it is necessary to set an address in addreg. as an address is set in addreg, the rom corr ection function is enabled for this register. if the cpu has the bus right, rom data is replaced when the value generated by the pc matches that of the address register. if the dmac has the bus right, rom data is replaced when a source or destination address generated by the dmac matches the value of the address register. for example, if an address is set in addreg0 and addreg3, the rom correction function is enabled for this area; match detection is performed on these registers, and data replacement is executed if there is a match. data replacement is not execute d for addreg1, addreg2, and addreg4 through addreg7. although the bit <31:5> ex ists in address registers, match detection is performed on a<20:5>. internal pro cessing is that data replacement is executed by multiplying the romcs signal showing a rom area by the result of a match detectio n operation performed by rom correction circuitry. if eight-word data is replaced, an address for rom correction can be established only on an eight-word boundary, and data is replaced in units of 32 bytes. if on ly part of 32-byte data must be replaced with different data, the addresses that do not need to be replaced must be overwritten with the same data as the one existing prior to data replacement. tmp19a64(rev1.1)-19-1
tmp19a64c1d addregn registers and ram areas assigned to them are as follows: register address ram area number of words addreg0 0xffff_e540 0xfffd_ff60 - 0xfffd_ff7f 8 addreg1 0xffff_e544 0xfffd_ff80 - 0xfffd_ff9f 8 addreg2 0xffff_e548 0xfffd_ffa0 - 0xfffd_ffbf 8 addreg3 0xffff_e54c 0xfffd_ffc0 - 0xfffd_ffdf 8 addreg4 0xffff_e550 0xfffd_ffe0 - 0xfffd_ffe3 1 addreg5 0xffff_e554 0xfffd_ffe4 - 0xfffd_ffe7 1 addreg6 0xffff_e558 0xfffd_ffe8 - 0xfffd_ffeb 1 addreg7 0xffff_e55c 0xfffd_ffec - 0xfffd_ffef 1 addreg8 0xffff_e560 0xfffd_fff0 - 0xfffd_ffe3 1 addreg9 0xffff_e564 0xfffd_fff4 - 0xfffd_ffe7 1 addrega 0xffff_e568 0xfffd_fff8 - 0xfffd_ffeb 1 addregb 0xffff_e56c 0xfffd_fffc - 0xfffd_ffef 1 tmp19a64(rev1.1)-19-2
tmp19a64c1d address registe r addregn comparison circuit selector operand address instruction address rom selector operand data instruction data tx19a processor bus interface circuit write detection & hold circuit of addregn authorize comparison ram conver- sion circuit internal bus fig. 19.2.1 rom correction system diagram tmp19a64(rev1.1)-19-3
tmp19a64c1d 19.3 registers (1) address registers 7 6 5 4 3 2 1 0 addreg0 bit symbol add07 add06 add05 (0xffff_e540) read/write r/w r after reset 0 0 0 1 1 1 1 1 15 14 13 12 11 10 9 8 bit symbol add015 add014 add013 add012 add011 add010 add09 add08 read/write r/w after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol add023 add022 add021 add020 add019 add018 add017 add016 read/write r/w after reset 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 bit symbol add031 add030 add029 add028 add027 add026 add025 add024 read/write r/w after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 addreg1 bit symbol add17 add16 add15 (0xffff_e544) read/write r/w r after reset 0 0 0 1 1 1 1 1 15 14 13 12 11 10 9 8 bit symbol add115 add114 add113 add112 add111 add110 add19 add18 read/write r/w after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol add123 add122 add121 add120 add119 add118 add117 add116 read/write r/w after reset 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 bit symbol add131 add130 add129 add128 add127 add126 add125 add124 read/write r/w after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 addreg2 bit symbol add27 add26 add25 (0xffff_e548) read/write r/w r after reset 0 0 0 1 1 1 1 1 15 14 13 12 11 10 9 8 bit symbol add215 add214 add213 add212 add211 add210 add29 add28 read/write r/w after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol add223 add222 add221 add220 add219 add218 add217 add216 read/write r/w after reset 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 bit symbol add231 add230 add229 add228 add227 add226 add225 add224 read/write r/w after reset 0 0 0 0 0 0 0 0 tmp19a64(rev1.1)-19-4
tmp19a64c1d 7 6 5 4 3 2 1 0 addreg3 bit symbol add37 add36 add35 (0xffff_e54c) read/write r/w r after reset 0 0 0 1 1 1 1 1 15 14 13 12 11 10 9 8 bit symbol add315 add314 add313 add312 add311 add310 add39 add38 read/write r/w after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol add323 add322 add321 add320 add319 add318 add317 add316 read/write r/w after reset 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 bit symbol add331 add330 add329 add328 add327 add326 add325 add324 read/write r/w after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 addreg4 bit symbol add47 add46 add45 add44 add43 add42 (0xffff_e550) read/write r/w r after reset 0 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8 bit symbol add415 add414 add413 add412 add411 add410 add49 add48 read/write r/w after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol add423 add422 add421 add420 add419 add418 add417 add416 read/write r/w after reset 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 bit symbol add431 add430 add429 add428 add427 add426 add425 add424 read/write r/w after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 addreg5 bit symbol add57 add56 add55 add54 add53 add52 (0xffff_e554) read/write r/w r after reset 0 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8 bit symbol add515 add514 add513 add512 add511 add510 add59 add58 read/write r/w after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol add523 add522 add521 add520 add519 add518 add517 add516 read/write r/w after reset 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 bit symbol add531 add530 add529 add528 add527 add526 add525 add524 read/write r/w after reset 0 0 0 0 0 0 0 0 tmp19a64(rev1.1)-19-5
tmp19a64c1d 7 6 5 4 3 2 1 0 addreg6 bit symbol add67 add66 add65 add64 add63 add62 (0xffff_e558) read/write r/w r after reset 0 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8 bit symbol add615 add614 add613 add612 add611 add610 add69 add68 read/write r/w after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol add623 add622 add621 add620 add619 add618 add617 add616 read/write r/w after reset 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 bit symbol add631 add630 add629 add628 add627 add626 add625 add624 read/write r/w after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 addreg7 bit symbol add77 add76 add75 add74 add73 add72 (0xffff_e55c) read/write r/w r after reset 0 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8 bit symbol add715 add714 add713 add712 add711 add710 add79 add78 read/write r/w after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol add723 add722 add721 add720 add719 add718 add717 add716 read/write r/w after reset 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 bit symbol add731 add730 add729 add728 add727 add726 add725 add724 read/write r/w after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 addreg8 bit symbol add87 add86 add85 add84 add83 add82 (0xffff_e560) read/write r/w r after reset 0 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8 bit symbol add815 add814 add813 add812 add811 add810 add89 add88 read/write r/w after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol add823 add822 add821 add820 add819 add818 add817 add816 read/write r/w after reset 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 bit symbol add831 add830 add829 add828 add827 add826 add825 add824 read/write r/w after reset 0 0 0 0 0 0 0 0 tmp19a64(rev1.1)-19-6
tmp19a64c1d 7 6 5 4 3 2 1 0 addreg9 bit symbol add97 add96 add95 add94 add93 add92 (0xffff_e564) read/write r/w r after reset 0 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8 bit symbol add915 add914 add913 add912 add911 add910 add99 add98 read/write r/w after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol add923 add922 add921 add920 add919 add918 add917 add916 read/write r/w after reset 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 bit symbol add931 add930 add929 add928 add927 add926 add925 add924 read/write r/w after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 addrega bit symbol adda7 adda6 adda5 adda4 adda3 adda2 (0xffff_e568) read/write r/w r after reset 0 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8 bit symbol adda15 adda14 adda13 adda12 adda11 adda10 adda9 adda8 read/write r/w after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol adda23 adda22 adda21 adda20 adda19 adda18 adda17 adda16 read/write r/w after reset 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 bit symbol adda31 adda30 adda29 adda28 adda27 adda26 adda25 adda24 read/write r/w after reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 addregb bit symbol addb7 addb6 addb5 addb4 addb3 addb2 (0xffff_e56c) read/write r/w r after reset 0 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8 bit symbol addb15 addb14 addb13 addb12 addb11 addb10 addb9 addb8 read/write r/w after reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol addb23 addb22 addb21 addb20 addb19 addb18 addb17 addb16 read/write r/w after reset 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 bit symbol addb31 addb30 addb29 addb28 addb27 addb26 addb25 addb24 read/write r/w after reset 0 0 0 0 0 0 0 0 tmp19a64(rev1.1)-19-7
tmp19a64c1d (note 1) data cannot be transferred by dma to the address register. however, data can be transferred by dma to the ram area where data for replacement is placed. the rom correction function supports data replacement for both cpu and dma access. (note 2) writing back the initial value "0x00" allows data at the reset address to be replaced. tmp19a64(rev1.1)-19-8
tmp19a64c1d tmp19a64 (rev1.1) -20-1 20. security function 20.1 general this device is implemented with the rom security functi on for the internal rom (fl ash) area as well as the dsu security function to inhibit use of dsu (dsu-probes). the following three security functions are available: ? flash security ? rom security ? dsu security 20.2 features 20.2.1 flash security the flash security function refers to the condition wh ere all the memory areas are protected through the automatic protection bit programming function to use the flcs b its inhibiting write and erase operations of the internal rom data for individual protection areas (in 512 kb blocks). in this case, the flash memory cannot be read fr om any area outside the flash memory such as the internal ram areas where the protection bit erase command cannot be accepted. after this, no command writing can be performed normally. the flash security function is al so a function to be necessary in enabling the rom security and dsu security functions. when the automatic protection bit erase command is execut ed while the system is in a secure condition, the flash memory is automatically initialized within the de vice. therefore, be sufficiently careful in making a transition to a secure state. 20.2.2 rom security the rom security function can inhibit data write/read operations to/from the internal rom. this function is used together with the flash security function. although the pc of ram ar ea instructions that have been repl aced from the rom ar ea through the rom correction function indicates an address in the flash rom area, it is actually in the ram area and thus data cannot be read in the condition rom s ecurity is in place. for reading data using an instruction in the ram area that has been replaced from the rom area, some sp ecial method such as to use a program in the rom area to write the data value into ram will be necessary. when the rom security is applied to the rom area, the following operations are inhibited: ? operation to load or store rom area data us ing an instruction placed outside the rom area ? dmac data transfer of rom area data ? ejtag based operation to load or store rom area data ? boot rom operation to load or store rom area data ? flash writer operation to load or store rom area data ? access to security related registers (romse c1 and romsec2) in the rom area using an instruction placed outside the rom area. ? execution of any flash command sequence other than the automatic block protection clear command and automatic block security clear comm and in the writer mode and any flash command sequence in the single mode or boot mode that specifies an address in the rom area
tmp19a64c1d tmp19a64 (rev1.1) -20-2 even when the rom security is applied to the rom area, the following operations can be performed: ? loading of rom area data using an instruction placed in the rom area ? loading of data outside the rom area to use an instruction placed in any area ? branch instruction to jump to the rom area to use an instruction placed in any area ? pc trace (with some limitations) and break operations in the rom area to use ejtag 20.2.3 dsu security the dsu security function prevents eas y reading of the internal flash memory by a third party other than the authorized user when an onb oard dsu probe is used. by enabling the dsu security function, it becomes impossible to read the internal flash memory from a dsu probe. this function is used together with the flash security function.
tmp19a64c1d 20.3 outline security configur ation and correspondence table chip 0 chip 1 protection bits flcs if "1111," romsec1 rom security flash security dsusec1 dsu security cs_dmac generation of bus error exception 19a64f20a when dmac register is written from outside internal rom fig. 21.3.1 various security conditions (outline) table 21.3.1 various security conditions in each mode protection bit setting, flcs 1111 1111 rom security enable bit, romsec1 1 0 don?t care dsu security enable bit, dsus ec1 1 0 1 0 don?t care flash security state on off rom security state on off off dsu security state on off on off off flash read from the internal rom { { { { { flash read from outside the internal rom *1 *1 { { { rom security enable clear (from rom) { { { rom security enable clear (from outside rom) *2 *2 { dsu security enable clear (from rom) { { { dsu security enable clear (from outside rom) *3 { { generation of protection bit erase command *4 *4 { *8 { *8 { generation of command other than protection bit erase command *5 *5 *7 *7 *9 write to dmac configuration register (from rom) { { { { { single/single boot mode write to dmac configuration register (from outside rom) *6 *6 { { { flash read *1 *1 *1 *1 { generation of protection bit erase command { *8 { *8 { *8 { *8 *9 writer mode generation of command other than protection bit erase command *7 *7 *7 *7 *9 *1 : always reads "0x00000098." *2 : masks the stored data (registe r cannot be written or cleared.) *3 : masks the stored data (registe r cannot be written or cleared.) *4 : command address is masked and the fl ash memory cannot recognize the command. *5 : command address is masked and the fl ash memory cannot recognize the command. *6 : bus error exceptions are generate d. (when set to dmac register.) *7 : commands are not recognized because of the flash security state. *8 : commands result in flash area erase and protection bit erase operations because of the flash security state. *9 : command conversion is performed in the flash interface ac cording to the protection bit status and input command. tmp19a64 (rev1.1) -20-3
tmp19a64c1d tmp19a64 (rev1.1) -20-4 20.4 register flash control/ status register this resister is used to monitor the status of the flash memory and to indicate the block protection status. table 21.3.2 flash control register 7 6 5 4 3 2 1 0 flcs bit symbol protect3 protect2 protect1 protect0 romtype prgb rdy/bsy (0xffff_e520) read/write r r r r/w r after power on reset 0 0 0 0 0 0 0 1 function protection area setting (in 512 kb blocks) 0000: no blocks are protected xxx1: area 0 is protected xx1x: area 1 is protected x1xx: area 2 is protected 1xxx: area 3 is protected rom id bit 0: flash 1: mrom programming bit 0: already issued 1: issue ready/busy 0: in operation 1: finished operation 15 14 13 12 11 10 9 8 bit symbol read/write r after power on reset 0 0 0 0 0 0 0 0 function 23 22 21 20 19 18 17 16 bit symbol read/write r after power on reset 0 0 0 0 0 0 0 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r after power on reset 0 0 0 0 0 0 0 0 function bit 0: ready/busy flag bit the rdy/bsy output is provided as a means to monitor the status of automatic operation. this bit is a function bit for the cpu to monitor the function. when th e flash memory is in automatic operation, it outputs "0" to indicate that it is busy. when the automatic operation is terminated, it returns to the ready state and outputs "1" to accept the next command. if the automatic operation has failed, this bit maintains the "0" output. it returns to "1" upon power on. (note) be sure to confirm the ready status whenever a command is to be issued. issuing a command while the device is busy may result in a situation where any further command inputs are rejected in addition to the fact that the command cannot be transferred correctly. in such a case, restore the system by using system reset or a reset command. bit 1: programming bit this bit notifies the flash interface that a co mmand is to be issued to the flash memory. be sure to set this bit to "1" whenever a command is to be issued to the internal flash memory. also, when all commands have been issued, set this bit to "0" after c onfirming that the bit has been set to "1." bit 2: rom type identification bit this bit is read after reset to identify wh ether the rom is a flash rom or a mask rom. flash rom: "0" mask rom: "1" bits [7:4]: protection bits (x: can be set to any combination of areas) each of the protection bits (4 bits) represents the protection status of th e corresponding area. when a bit is set to "1," it indicates th at the area corresponding to the bit is protecte d. when the area is protected, data cannot be written into it.
tmp19a64c1d tmp19a64 (rev1.1) -20-5 table 21.3.3 rom security register 7 6 5 4 3 2 1 0 romsec1 bit symbol rsecon (0xffff_e518) read/write r r/w after power on reset 0 1 function always reads "0." rom rom security 1: on 0: off (note) 15 14 13 12 11 10 9 8 bit symbol read/write r after power on reset 0 function always reads "0." 23 22 21 20 19 18 17 16 bit symbol read/write r after power on reset 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r after power on reset 0 function always reads "0." (note) this register can be initialized only by a power on reset. normal reset inputs cannot reset the register. (note) this register must be 32-bit accessed.
tmp19a64c1d tmp19a64 (rev1.1) -20-6 table 21.3.4 security lock register 7 6 5 4 3 2 1 0 romsec2 bit symbol (0xffff_e51c) read/write w after reset undefined function refer to the note. 15 14 13 12 11 10 9 8 b i t s y m b o l read/write w after reset undefined function refer to the note. 23 22 21 20 19 18 17 16 b i t s y m b o l read/write w after reset undefined function refer to the note. 31 30 29 28 27 26 25 24 b i t s y m b o l read/write w after reset undefined function refer to the note. (note) after setting romsec1 , setting "0x0000_003d" to this register sets the value to romsec1 . (note) when rom security is applied to a rom area, the romsec1 and romsec2 registers can be accessed only from an instruction placed in the rom area. (note) this register must be 32-bit accessed. (note) this register is a write-only register. any value read is undefined.
tmp19a64c1d tmp19a64 (rev1.1) -20-7 table 21.3.5 dsu security mode register 7 6 5 4 3 2 1 0 dsusec1 bit symbol dsuoff (0xffff_e510) read/write r r/w after power on reset 0 1 function always reads "0." 1: dsu disable 0: dsu enable 15 14 13 12 11 10 9 8 bit symbol read/write r after power on reset 0 function always reads "0." 23 22 21 20 19 18 17 16 bit symbol read/write r after power on reset 0 function 31 30 29 28 27 26 25 24 bit symbol read/write r after power on reset 0 function always reads "0." (note) this register can be initialized only by a power on reset. normal reset inputs cannot reset the register. (note) this register must be 32-bit accessed. table 21.3.6 dsu security control register 7 6 5 4 3 2 1 0 dsusec2 bit symbol dsecode07 dsecode06 dsecode05 dsecode04 dsecode03 dsecode02 dsecode01 dsecode00 (0xffff_e514) read/write w after reset 0 function write "0x0000_00c5." 15 14 13 12 11 10 9 8 bit symbol dsecode15 dsecode14 dsecode13 dsecode12 dsecode11 dsecode10 dsecode09 dsecode08 read/write w after reset 0 function write "0x0000_00c5." 23 22 21 20 19 18 17 16 bit symbol dsecode23 dsecode22 dsecode21 dsecode20 dsecode19 dsecode18 dsecode17 dsecode16 read/write w after reset 0 function write "0x0000_00c5." 31 30 29 28 27 26 25 24 bit symbol dsecode31 dsecode30 dsecode29 dsecode28 dsecode27 dsecode26 dsecode25 dsecode24 read/write w after reset 0 function write "0x0000_00c5." (note) this register must be 32-bit accessed. (note) this register is a write-only register. any value read is undefined.
tmp19a64c1d tmp19a64 (rev1.1) -20-8 20.5 setting security configuration if it is necessary to rewrite the flash memory or protectio n bits while the device is in a secure state, either perform the automatic protection bit erase operation or clear the rom security function. while the dsu security is applied, any dsu cannot be used. the setting is necessary to make dsu- probe available beforehand if an automatic protection bit programming is executed to result in a flash security state. when the automatic protection bit erase command is executed while the system is in the flash security mode, the flash memory is automatically initialized within the devi ce. therefore, be sufficiently careful in making a transition to a secure state. 20.5.1 flash security setting or clearing of flash security is made using a command sequence to the flash memory to use the protection bit programming command. refer to command sequence descriptions in the section describing flash memory operation for more details. 20.5.2 rom security in order to prevent the rom security function from being accidentally removed by system runaway, etc., a double action method is used to set or clear the rom security function. to make rom security functional, first set the rom security register romsec1 to "1" and then write the security code "0x0000_003d" to the rom security lock register ro msec2. similarly, when the rom security function is to be cleared, first set the rom security regi ster romsec1 to "0" and then write the security code "0x0000_003d" to the ro m security lock register romsec2. (note) the rom security register has a power on reset circuit and the bit is set to "1" after power is turned on. if the flash security function is in place at this point, the rom security function is automatically enabled to inhibit data write/read operations to/from the internal rom. 20.5.3 dsu security dsu enable/disable (enables or disables use of dsu probes for debugging) in order to prevent the dsu inhibit function from being accidentally removed by system runaway, etc., a double action method is used to clear the dsu inhibit function. so, first set the dsu security mode register dsusec1 to "0" and then write the security code "0x0000_00c5" to the dsu security control register dsusec2. then, debugging to use a dsu probe is allowed. while power to the device is still applied, setting dsusec1 to "1" and wr iting "0x0000_00c5" to the dsusec2 register will enable the security function again. (note) the dsu security mode register has a power on reset circuit and the bit is set to "1" after power is turned on. if the flash security function is in place at this point, the dsu security function is automatically enabled and it becomes impossible to read the internal flash memory from any dsu probe.
tmp19a64c1d 20.5.4 rom security regi ster: romsec1 the rom security register is provided with a power on re set circuit. note that the data to be read from the romsec1 bit is different from the original data written to the register. the outline schematic diagram is shown below: tmp19a64 (rev1.1) -20-9 20.5.5 dsu security mode register: dsusec1 the dsu security mode register is pr ovided with a power on reset circuit. note that the data to be read from the dsusec1 bit is different from the original data written to the register. the outline schematic diagram is shown below: dsusec1 write dsusec1 write data clk reset power on reset dsu security flash security dsusec1 read data dsusec2 = 0x0000_00c5 in the rom security state, any access from outside the internal rom is inhibited. d q sd dq sd romsec1 write romsec1 write data clk reset power on reset rom security flash security romsec1 read data dq dq sd sd romsec2 = 0x0000_003d in the rom security state, any access from outside the rom is inhibited.
tmp19a64c1d tmp19a64 (rev1.1) -21-1 21. table of special function registers special function registers are a llocated to an 8k-byte address space from ffffe000h to ffffffffh. [1] port registers [2] watchdog timer [3] 16-bit timer [4] i 2 cbus/serial channel [5] uart/serial channel [6] 10-bit a/d converter [7] key-on wake-up [8] 32-bit input capture [9] 32-bit compare [10] interrupt controller [11] dma controller [12] chip select/wait controller [13] access control [14] security control [15] flash control [16] rom correction [17] clock timer [18] clock generator (note) 0xffff_f000 to 0xffff _ffff are a little-endian area. 0xffff_e000 to 0xffff_efff are a bi-endian area. (note) for continuous 8-b it long registers, 16- or 32-bit access is possible. the use of 16- or 32-bit access requires that an even-number address be accessed and that an even-number address does not contain undefined areas.
tmp19a64c1d tmp19a64 (rev1.1) -21-2 little-endian [1] port registers adr register name adr register name adr register name fffff000h p0 fffff010h fffff020h p4cr 1h p1 1h 1h p4fc 2h p0cr 2h p2 2h 3h 3h 3h 4h p1cr 4h p2cr 4h 5h p1fc 5h p2fc 5h 6h 6h 6h 7h 7h 7h 8h 8h p3 8h p5 9h 9h 9h p6 ah ah p3cr ah bh bh p3fc bh ch ch ch p5cr dh dh dh p5fc eh eh p4 eh p6cr fh fh fh p6fc adr register name adr register name adr register name adr register name fffff040h p7 fffff050h pb fffff060h pf fffff070h pj 1h p8 1h pc 1h pg 1h pk 2h p9 2h pd 2h ph 2h 3h pa 3h pe 3h pi 3h 4h 4h pbcr 4h pfcr 4h pjcr 5h 5h pccr 5h pgcr 5h pkcr 6h 6h pdcr 6h phcr 6h 7h pacr 7h pecr 7h picr 7h 8h p7fc 8h pbfc 8h pffc 8h pjfc 9h p8fc 9h pcfc 9h pgfc 9h pkfc ah p9fc ah pdfc ah phfc ah bh pafc bh pefc bh pifc bh ch ch ch pfode ch dh dh pcode dh dh eh eh pdode eh eh fh fh peode fh fh adr register name adr register name fffff0c0h pl fffff0d0h pp 1h pm 1h pq 2h pn 2h 3h po 3h 4h plcr 4h ppcr 5h pmcr 5h pqcr 6h pncr 6h 7h pocr 7h 8h 8h ppfc 9h 9h ah ah bh pofc bh ch ch ppfc2 dh dh pqfc2 eh eh fh poode fh
tmp19a64c1d tmp19a64 (rev1.1) -21-3 little-endian [2] wdt adr register name fffff090h wdmod 1h wdcr 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh [3] 16-bit timer adr register name adr register name adr register name adr register name fffff140h tb0run fffff150h tb1run fffff160h tb2run fffff170h tb3run 1h tb0cr 1h tb1cr 1h tb2cr 1h tb3cr 2h tb0mod 2h tb1mod 2h tb2mod 2h tb3mod 3h tb0ffcr 3h tb1ffcr 3h tb2ffcr 3h tb3ffcr 4h tb0st 4h tb1st 4h tb2st 4h tb3st 5h 5h 5h 5h 6h tb0ucl 6h tb1ucl 6h tb2ucl 6h tb3ucl 7h tb0uch 7h tb1uch 7h tb2uch 7h tb3uch 8h tb0rg0l 8h tb1rg0l 8h tb2rg0l 8h tb3rg0l 9h tb0rg0h 9h tb1rg0h 9h tb2rg0h 9h tb3rg0h ah tb0rg1l ah tb1rg1l ah tb2rg1l ah tb3rg1l bh tb0rg1h bh tb1rg1h bh tb2rg1h bh tb3rg1h ch tb0cp0l ch tb1cp0l ch tb2cp0l ch tb3cp0l dh tb0cp0h dh tb1cp0h dh tb2cp0h dh tb3cp0h eh tb0cp1l eh tb1cp1l eh tb2cp1l eh tb3cp1l fh tb0cp1h fh tb1cp1h fh tb2cp1h fh tb3cp1h adr register name adr register name adr register name adr register name fffff180h tb4run fffff190h tb5run fffff1a0h tb6run fffff1b0h tb7run 1h tb4cr 1h tb5cr 1h tb6cr 1h tb7cr 2h tb4mod 2h tb5mod 2h tb6mod 2h tb7mod 3h tb4ffcr 3h tb5ffcr 3h tb6ffcr 3h tb7ffcr 4h tb4st 4h tb5st 4h tb6st 4h tb7st 5h 5h 5h 5h 6h tb4ucl 6h tb5ucl 6h tb6ucl 6h tb7ucl 7h tb4uch 7h tb5uch 7h tb6uch 7h tb7uch 8h tb4rg0l 8h tb5rg0l 8h tb6rg0l 8h tb7rg0l 9h tb4rg0h 9h tb5rg0h 9h tb6rg0h 9h tb7rg0h ah tb4rg1l ah tb5rg1l ah tb6rg1l ah tb7rg1l bh tb4rg1h bh tb5rg1h bh tb6rg1h bh tb7rg1h ch tb4cp0l ch tb5cp0l ch tb6cp0l ch tb7cp0l dh tb4cp0h dh tb5cp0h dh tb6cp0h dh tb7cp0h eh tb4cp1l eh tb5cp1l eh tb6cp1l eh tb7cp1l fh tb4cp1h fh tb5cp1h fh tb6cp1h fh tb7cp1h
tmp19a64c1d tmp19a64 (rev1.1) -21-4 little-endian adr register name adr register name adr register name fffff1c0h tb8run fffff1d0h tb9run fffff1e0h tbarun 1h tb8cr 1h tb9cr 1h tbacr 2h tb8mod 2h tb9mod 2h tbamod 3h tb8ffcr 3h tb9ffcr 3h tbaffcr 4h tb8st 4h tb9st 4h tbast 5h 5h 5h 6h tb8ucl 6h tb9ucl 6h tbaucl 7h tb8uch 7h tb9uch 7h tbauch 8h tb8rg0l 8h tb9rg0l 8h tbarg0l 9h tb8rg0h 9h tb9rg0h 9h tbarg0h ah tb8rg1l ah tb9rg1l ah tbarg1l bh tb8rg1h bh tb9rg1h bh tbarg1h ch tb8cp0l ch tb9cp0l ch tbacp0l dh tb8cp0h dh tb9cp0h dh tbacp0h eh tb8cp1l eh tb9cp1l eh tbacp1l fh tb8cp1h fh tb9cp1h fh tbacp1h [4] i2c/sio [5] uart/sio adr register name adr register name adr register name adr register name fffff250h sbicr1 fffff260h sc0buf fffff270h sc1buf fffff280h sc2buf 1h sbidbr 1h sc0cr 1h sc1cr 1h sc2cr 2h i2car 2h sc0mod0 2h sc1mod0 2h sc2mod0 3h sbicr2/sr 3h br0cr 3h br1cr 3h br2cr 4h sbibr0 4h br0add 4h br1add 4h br2add 5h 5h sc0mod1 5h sc1mod1 5h sc2mod1 6h 6h sc0mod2 6h sc1mod2 6h sc2mod2 7h sbicr0 7h sc0en 7h sc1en 7h sc2en 8h 8h sc0rfc 8h sc1rfc 8h sc2rfc 9h 9h sc0tfc 9h sc1tfc 9h sc2tfc ah ah sc0rst ah sc1rst ah sc2rst bh bh sc0tst bh sc1tst bh sc2tst ch ch sc0fcnf ch sc1fcnf ch sc2fcnf dh dh dh dh eh eh eh eh fh fh fh fh adr register name adr register name adr register name adr register name fffff290h sc3buf fffff2a0h sc4buf fffff2b0h sc5buf fffff2c0h sc6buf 1h sc3cr 1h sc4cr 1h sc5cr 1h sc6cr 2h sc3mod0 2h sc4mod0 2h sc5mod0 2h sc6mod0 3h br3cr 3h br4cr 3h br5cr 3h br6cr 4h br3add 4h br4add 4h br5add 4h br6add 5h sc3mod1 5h sc4mod1 5h sc5mod1 5h sc6mod1 6h sc3mod2 6h sc4mod2 6h sc5mod2 6h sc6mod2 7h sc3en 7h sc4en 7h sc5en 7h sc6en 8h sc3rfc 8h sc4rfc 8h sc5rfc 8h sc6rfc 9h sc3tfc 9h sc4tfc 9h sc5tfc 9h sc6tfc ah sc3rst ah sc4rst ah sc5rst ah sc6rst bh sc3tst bh sc4tst bh sc5tst bh sc6tst ch sc3fcnf ch sc4fcnf ch sc5fcnf ch sc6fcnf dh dh dh dh eh eh eh eh fh fh fh fh
tmp19a64c1d tmp19a64 (rev1.1) -21-5 little-endian [6] 10-bit adc [7] kwup adr register name adr register name adr register name adr register name fffff300h adreg08l fffff310h adregspl fffff360h kwupst0 fffff370h kwupst 1h adreg08h 1h adregsph 1h kwupst1 1h kuppup 2h adreg19l 2h adcomregl 2h kwupst2 2h 3h adreg19h 3h adcomregh 3h kwupst3 3h 4h adreg2al 4h admod0 4h kwupst4 4h 5h adreg2ah 5h admod1 5h kwupst5 5h 6h adreg3bl 6h admod2 6h kwupst6 6h 7h adreg3bh 7h admod3 7h kwupst7 7h 8h adreg4cl 8h admod4 8h 8h 9h adreg4ch 9h 9h 9h ah adreg5dl ah ah ah bh adreg5dh bh bh bh ch adreg6el ch adclk ch ch dh adreg6eh dh dh dh eh adreg7fl eh eh eh fh adreg7fh fh fh fh [8] 32-bit input capture adr register name adr register name adr register name fffff400h tccr fffff410h cap0cr fffff420h cap2cr 1h tbtrun 1h 1h 2h tbtcr 2h 2h 3h 3h 3h 4h tbtcap0 4h tccap0ll 4h tccap2ll 5h tbtcap1 5h tccap0lh 5h tccap2lh 6h tbtcap2 6h tccap0hl 6h tccap2hl 7h tbtcap3 7h tccap0hh 7h tccap2hh 8h tbtrdcap0 8h cap1cr 8h cap3cr 9h tbtrdcap1 9h 9h ah tbtrdcap2 ah ah bh tbtrdcap3 bh bh ch tcgim ch tccap1ll ch tccap3ll dh tcgst dh tccap1lh dh tccap3lh eh eh tccap1hl eh tccap3hl fh fh tccap1hh fh tccap3hh [9] 32-bit output compare adr register name adr register name adr register name adr register name fffff440h tccmp0ll fffff450h tccmp4ll fffff460h tccmp8ll fffff470h cmpctl0 1h tccmp0lh 1h tccmp4lh 1h tccmp8lh 1h cmpctl1 2h tccmp0hl 2h tccmp4hl 2h tccmp8hl 2h cmpctl2 3h tccmp0hh 3h tccmp4hh 3h tccmp8hh 3h cmpctl3 4h tccmp1ll 4h tccmp5ll 4h tccmp9ll 4h cmpctl4 5h tccmp1lh 5h tccmp5lh 5h tccmp9lh 5h cmpctl5 6h tccmp1hl 6h tccmp5hl 6h tccmp9hl 6h cmpctl6 7h tccmp1hh 7h tccmp5hh 7h tccmp9hh 7h cmpctl7 8h tccmp2ll 8h tccmp6ll 8h 8h cmpctl8 9h tccmp2lh 9h tccmp6lh 9h 9h cmpctl9 ah tccmp2hl ah tccmp6hl ah ah bh tccmp2hh bh tccmp6hh bh bh ch tccmp3ll ch tccmp7ll ch ch dh tccmp3lh dh tccmp7lh dh dh eh tccmp3hl eh tccmp7hl eh eh fh tccmp3hh fh tccmp7hh fh fh
tmp19a64c1d tmp19a64 (rev1.1) -21-6 little-endian [10] intc adr register name adr register name adr register name adr register name ffffe000h imc0 ffffe010h imc4 ffffe020h imc8 ffffe030h imcc 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h imc1 4h imc5 4h imc9 4h imcd 5h ditto 5h ditto 5h ditto 5h ditto 6h ditto 6h ditto 6h ditto 6h ditto 7h ditto 7h ditto 7h ditto 7h ditto 8h imc2 8h imc6 8h imca 8h imce 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch imc3 ch imc7 ch imcb ch imcf dh ditto dh ditto dh ditto dh ditto eh ditto eh ditto eh ditto eh ditto fh ditto fh ditto fh ditto fh ditto adr register name adr register name adr register name ffffe040h ivr ffffe060h intclr ffffe100h 1h ditto 1h ditto 1h 2h ditto 2h ditto 2h 3h ditto 3h ditto 3h 4h 4h 4h 5h 5h 5h 6h 6h 6h 7h 7h 7h 8h 8h 8h 9h 9h 9h ah ah ah bh bh bh ch ch ch ilev dh dh dh ditto eh eh eh ditto fh fh fh ditto
tmp19a64c1d tmp19a64 (rev1.1) -21-7 little-endian [11] dmac adr register name adr register name adr register name adr register name ffffe200h ccr0 ffffe210h bcr0 ffffe220h ccr1 ffffe230h bcr1 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h csr0 4h 4h csr1 4h 5h ditto 5h 5h ditto 5h 6h ditto 6h 6h ditto 6h 7h ditto 7h 7h ditto 7h 8h sar0 8h dtcr0 8h sar1 8h dtcr1 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch dar0 ch ch dar1 ch dh ditto dh dh ditto dh eh ditto eh eh ditto eh fh ditto fh fh ditto fh adr register name adr register name adr register name adr register name ffffe240h ccr2 ffffe250h bcr2 ffffe260h ccr3 ffffe270h bcr3 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h csr2 4h 4h csr3 4h 5h ditto 5h 5h ditto 5h 6h ditto 6h 6h ditto 6h 7h ditto 7h 7h ditto 7h 8h sar2 8h dtcr2 8h sar3 8h dtcr3 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch dar2 ch ch dar3 ch dh ditto dh dh ditto dh eh ditto eh eh ditto eh fh ditto fh fh ditto fh adr register name adr register name adr register name adr register name ffffe280h ccr4 ffffe290h bcr4 ffffe2a0h ccr5 ffffe2b0h bcr5 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h csr4 4h 4h csr5 4h 5h ditto 5h 5h ditto 5h 6h ditto 6h 6h ditto 6h 7h ditto 7h 7h ditto 7h 8h sar4 8h dtcr4 8h sar5 8h dtcr5 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch dar4 ch ch dar5 ch dh ditto dh dh ditto dh eh ditto eh eh ditto eh fh ditto fh fh ditto fh
tmp19a64c1d tmp19a64 (rev1.1) -21-8 little-endian adr register name adr register name adr register name adr register name ffffe2c0h ccr6 ffffe2d0h bcr6 ffffe2e0h ccr7 ffffe2f0h bcr7 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h csr6 4h 4h csr7 4h 5h ditto 5h 5h ditto 5h 6h ditto 6h 6h ditto 6h 7h ditto 7h 7h ditto 7h 8h sar6 8h dtcr6 8h sar7 8h dtcr7 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch dar6 ch ch dar7 ch dh ditto dh dh ditto dh eh ditto eh eh ditto eh fh ditto fh fh ditto fh adr register name ffffe300h dcr 1h ditto 2h ditto 3h ditto 4h rsr 5h ditto 6h ditto 7h ditto 8h 9h ah bh ch dhr dh ditto eh ditto fh ditto
tmp19a64c1d tmp19a64 (rev1.1) -21-9 little-endian [12] cs/wait controller adr register name adr register name adr register name ffffe400h bma0 ffffe410h bma4 ffffe480h b01cs 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 4h bma1 4h bma5 4h b23cs 5h ditto 5h ditto 5h ditto 6h ditto 6h ditto 6h ditto 7h ditto 7h ditto 7h ditto 8h bma2 8h 8h b45cs 9h ditto 9h 9h ditto ah ditto ah ah ditto bh ditto bh bh ditto ch bma3 ch ch bexcs dh ditto dh dh ditto eh ditto eh eh ditto fh ditto fh fh ditto [13] access control [14] security control [15] flash control adr register name adr register name adr register name ffffe500h pfbwait ffffe510h dsusec1 ffffe520h flcs 1h 1h ditto 1h ditto 2h 2h ditto 2h ditto 3h 3h ditto 3h ditto 4h 4h dsusec2 4h 5h 5h ditto 5h 6h 6h ditto 6h 7h 7h ditto 7h 8h 8h romsec1 8h 9h 9h 9h ah ah ah bh bh bh ch ch romsec2 ch dh dh dh eh eh eh fh fh fh [16] rom correction adr register name adr register name adr register name ffffe540h addreg0 ffffe550h addreg4 ffffe560h addreg8 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 4h addreg1 4h addreg5 4h addreg9 5h ditto 5h ditto 5h ditto 6h ditto 6h ditto 6h ditto 7h ditto 7h ditto 7h ditto 8h addreg2 8h addreg6 8h addrega 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto ch addreg3 ch addreg7 ch addregb dh ditto dh ditto dh ditto eh ditto eh ditto eh ditto fh ditto fh ditto fh ditto
tmp19a64c1d tmp19a64 (rev1.1) -21-10 little-endian [17] clock timer adr register name adr register name ffffe700h rtcflg ffffe710h 1h ditto 1h 2h ditto 2h 3h ditto 3h 4h rtccr 4h 5h ditto 5h 6h ditto 6h 7h ditto 7h 8h rtcreg 8h 9h ditto 9h ah ditto ah bh ditto bh ch ch dh dh eh eh fh fh [18] cg adr register name adr register name adr register name ffffee00h syscr0 ffffee10h imcga ffffee20h eicrcg 1h syscr1 1h ditto 1h ditto 2h syscr2 2h ditto 2h ditto 3h syscr3 3h ditto 3h ditto 4h 4h imcgb 4h nmiflg 5h 5h ditto 5h ditto 6h 6h ditto 6h ditto 7h 7h ditto 7h ditto 8h 8h imcgc 8h 9h 9h ditto 9h ah ah ditto ah bh bh ditto bh ch ch imcgd ch dh dh ditto dh eh eh ditto eh fh fh ditto fh
tmp19a64c1d tmp19a64 (rev1.1) -21-11 big-endian [1] port registers adr register name adr register name adr register name fffff000h p0 fffff010h fffff020h p4cr 1h p1 1h 1h p4fc 2h p0cr 2h p2 2h 3h 3h 3h 4h p1cr 4h p2cr 4h 5h p1fc 5h p2fc 5h 6h 6h 6h 7h 7h 7h 8h 8h p3 8h p5 9h 9h 9h p6 ah ah p3cr ah bh bh p3fc bh ch ch ch p5cr dh dh dh p5fc eh eh p4 eh p6cr fh fh fh p6fc adr register name adr register name adr register name adr register name fffff040h p7 fffff050h pb fffff060h pf fffff070h pj 1h p8 1h pc 1h pg 1h pk 2h p9 2h pd 2h ph 2h 3h pa 3h pe 3h pi 3h 4h 4h pbcr 4h pfcr 4h pjcr 5h 5h pccr 5h pgcr 5h pkcr 6h 6h pdcr 6h phcr 6h 7h pacr 7h pecr 7h picr 7h 8h p7fc 8h pbfc 8h pffc 8h pjfc 9h p8fc 9h pcfc 9h pgfc 9h pkfc ah p9fc ah pdfc ah phfc ah bh pafc bh pefc bh pifc bh ch ch ch pfode ch dh dh pcode dh dh eh eh pdode eh eh fh fh peode fh fh adr register name adr register name fffff0c0h pl fffff0d0h pp 1h pm 1h pq 2h pn 2h 3h po 3h 4h plcr 4h ppcr 5h pmcr 5h pqcr 6h pncr 6h 7h pocr 7h 8h 8h ppfc 9h 9h ah ah bh pofc bh ch ch ppfc2 dh dh pqfc2 eh eh fh poode fh
tmp19a64c1d tmp19a64 (rev1.1) -21-12 big-endian [2] wdt adr register name fffff090h wdmod 1h wdcr 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh [3] 16-bit timer adr register name adr register name adr register name adr register name fffff140h tb0run fffff150h tb1run fffff160h tb2run fffff170h tb3run 1h tb0cr 1h tb1cr 1h tb2cr 1h tb3cr 2h tb0mod 2h tb1mod 2h tb2mod 2h tb3mod 3h tb0ffcr 3h tb1ffcr 3h tb2ffcr 3h tb3ffcr 4h tb0st 4h tb1st 4h tb2st 4h tb3st 5h 5h 5h 5h 6h tb0ucl 6h tb1ucl 6h tb2ucl 6h tb3ucl 7h tb0uch 7h tb1uch 7h tb2uch 7h tb3uch 8h tb0rg0l 8h tb1rg0l 8h tb2rg0l 8h tb3rg0l 9h tb0rg0h 9h tb1rg0h 9h tb2rg0h 9h tb3rg0h ah tb0rg1l ah tb1rg1l ah tb2rg1l ah tb3rg1l bh tb0rg1h bh tb1rg1h bh tb2rg1h bh tb3rg1h ch tb0cp0l ch tb1cp0l ch tb2cp0l ch tb3cp0l dh tb0cp0h dh tb1cp0h dh tb2cp0h dh tb3cp0h eh tb0cp1l eh tb1cp1l eh tb2cp1l eh tb3cp1l fh tb0cp1h fh tb1cp1h fh tb2cp1h fh tb3cp1h adr register name adr register name adr register name adr register name fffff180h tb4run fffff190h tb5run fffff1a0h tb6run fffff1b0h tb7run 1h tb4cr 1h tb5cr 1h tb6cr 1h tb7cr 2h tb4mod 2h tb5mod 2h tb6mod 2h tb7mod 3h tb4ffcr 3h tb5ffcr 3h tb6ffcr 3h tb7ffcr 4h tb4st 4h tb5st 4h tb6st 4h tb7st 5h 5h 5h 5h 6h tb4ucl 6h tb5ucl 6h tb6ucl 6h tb7ucl 7h tb4uch 7h tb5uch 7h tb6uch 7h tb7uch 8h tb4rg0l 8h tb5rg0l 8h tb6rg0l 8h tb7rg0l 9h tb4rg0h 9h tb5rg0h 9h tb6rg0h 9h tb7rg0h ah tb4rg1l ah tb5rg1l ah tb6rg1l ah tb7rg1l bh tb4rg1h bh tb5rg1h bh tb6rg1h bh tb7rg1h ch tb4cp0l ch tb5cp0l ch tb6cp0l ch tb7cp0l dh tb4cp0h dh tb5cp0h dh tb6cp0h dh tb7cp0h eh tb4cp1l eh tb5cp1l eh tb6cp1l eh tb7cp1l fh tb4cp1h fh tb5cp1h fh tb6cp1h fh tb7cp1h
tmp19a64c1d tmp19a64 (rev1.1) -21-13 big-endian adr register name adr register name adr register name fffff1c0h tb8run fffff1d0h tb9run fffff1e0h tbarun 1h tb8cr 1h tb9cr 1h tbacr 2h tb8mod 2h tb9mod 2h tbamod 3h tb8ffcr 3h tb9ffcr 3h tbaffcr 4h tb8st 4h tb9st 4h tbast 5h 5h 5h 6h tb8ucl 6h tb9ucl 6h tbaucl 7h tb8uch 7h tb9uch 7h tbauch 8h tb8rg0l 8h tb9rg0l 8h tbarg0l 9h tb8rg0h 9h tb9rg0h 9h tbarg0h ah tb8rg1l ah tb9rg1l ah tbarg1l bh tb8rg1h bh tb9rg1h bh tbarg1h ch tb8cp0l ch tb9cp0l ch tbacp0l dh tb8cp0h dh tb9cp0h dh tbacp0h eh tb8cp1l eh tb9cp1l eh tbacp1l fh tb8cp1h fh tb9cp1h fh tbacp1h [4] i2c/sio [5] uart/sio adr register name adr register name adr register name adr register name fffff250h sbicr1 fffff260h sc0buf fffff270h sc1buf fffff280h sc2buf 1h sbidbr 1h sc0cr 1h sc1cr 1h sc2cr 2h i2car 2h sc0mod0 2h sc1mod0 2h sc2mod0 3h sbicr2/sr 3h br0cr 3h br1cr 3h br2cr 4h sbibr0 4h br0add 4h br1add 4h br2add 5h 5h sc0mod1 5h sc1mod1 5h sc2mod1 6h 6h sc0mod2 6h sc1mod2 6h sc2mod2 7h sbicr0 7h sc0en 7h sc1en 7h sc2en 8h 8h sc0rfc 8h sc1rfc 8h sc2rfc 9h 9h sc0tfc 9h sc1tfc 9h sc2tfc ah ah sc0rst ah sc1rst ah sc2rst bh bh sc0tst bh sc1tst bh sc2tst ch ch sc0fcnf ch sc1fcnf ch sc2fcnf dh dh dh dh eh eh eh eh fh fh fh fh adr register name adr register name adr register name adr register name fffff290h sc3buf fffff2a0h sc4buf fffff2b0h sc5buf fffff2c0h sc6buf 1h sc3cr 1h sc4cr 1h sc5cr 1h sc6cr 2h sc3mod0 2h sc4mod0 2h sc5mod0 2h sc6mod0 3h br3cr 3h br4cr 3h br5cr 3h br6cr 4h br3add 4h br4add 4h br5add 4h br6add 5h sc3mod1 5h sc4mod1 5h sc5mod1 5h sc6mod1 6h sc3mod2 6h sc4mod2 6h sc5mod2 6h sc6mod2 7h sc3en 7h sc4en 7h sc5en 7h sc6en 8h sc3rfc 8h sc4rfc 8h sc5rfc 8h sc6rfc 9h sc3tfc 9h sc4tfc 9h sc5tfc 9h sc6tfc ah sc3rst ah sc4rst ah sc5rst ah sc6rst bh sc3tst bh sc4tst bh sc5tst bh sc6tst ch sc3fcnf ch sc4fcnf ch sc5fcnf ch sc6fcnf dh dh dh dh eh eh eh eh fh fh fh fh
tmp19a64c1d tmp19a64 (rev1.1) -21-14 big-endian [6] 10-bit adc [7] kwup adr register name adr register name adr register name adr register name fffff300h adreg08l fffff310h adregspl fffff360h kwupst0 fffff370h kwupst 1h adreg08h 1h adregsph 1h kwupst1 1h kuppup 2h adreg19l 2h adcomregl 2h kwupst2 2h 3h adreg19h 3h adcomregh 3h kwupst3 3h 4h adreg2al 4h admod0 4h kwupst4 4h 5h adreg2ah 5h admod1 5h kwupst5 5h 6h adreg3bl 6h admod2 6h kwupst6 6h 7h adreg3bh 7h admod3 7h kwupst7 7h 8h adreg4cl 8h admod4 8h 8h 9h adreg4ch 9h 9h 9h ah adreg5dl ah ah ah bh adreg5dh bh bh bh ch adreg6el ch adclk ch ch dh adreg6eh dh dh dh eh adreg7fl eh eh eh fh adreg7fh fh fh fh [8] 32-bit input capture adr register name adr register name adr register name fffff400h tccr fffff410h cap0cr fffff420h cap2cr 1h tbtrun 1h 1h 2h tbtcr 2h 2h 3h 3h 3h 4h tbtcap0 4h tccap0ll 4h tccap2ll 5h tbtcap1 5h tccap0lh 5h tccap2lh 6h tbtcap2 6h tccap0hl 6h tccap2hl 7h tbtcap3 7h tccap0hh 7h tccap2hh 8h tbtrdcap0 8h cap1cr 8h cap3cr 9h tbtrdcap1 9h 9h ah tbtrdcap2 ah ah bh tbtrdcap3 bh bh ch tcgim ch tccap1ll ch tccap3ll dh tcgst dh tccap1lh dh tccap3lh eh eh tccap1hl eh tccap3hl fh fh tccap1hh fh tccap3hh [9] 32-bit output compare adr register name adr register name adr register name adr register name fffff440h tccmp0ll fffff450h tccmp4ll fffff460h tccmp8ll fffff470h cmpctl0 1h tccmp0lh 1h tccmp4lh 1h tccmp8lh 1h cmpctl1 2h tccmp0hl 2h tccmp4hl 2h tccmp8hl 2h cmpctl2 3h tccmp0hh 3h tccmp4hh 3h tccmp8hh 3h cmpctl3 4h tccmp1ll 4h tccmp5ll 4h tccmp9ll 4h cmpctl4 5h tccmp1lh 5h tccmp5lh 5h tccmp9lh 5h cmpctl5 6h tccmp1hl 6h tccmp5hl 6h tccmp9hl 6h cmpctl6 7h tccmp1hh 7h tccmp5hh 7h tccmp9hh 7h cmpctl7 8h tccmp2ll 8h tccmp6ll 8h 8h cmpctl8 9h tccmp2lh 9h tccmp6lh 9h 9h cmpctl9 ah tccmp2hl ah tccmp6hl ah ah bh tccmp2hh bh tccmp6hh bh bh ch tccmp3ll ch tccmp7ll ch ch dh tccmp3lh dh tccmp7lh dh dh eh tccmp3hl eh tccmp7hl eh eh fh tccmp3hh fh tccmp7hh fh fh
tmp19a64c1d tmp19a64 (rev1.1) -21-15 big-endian [10] intc adr register name adr register name adr register name adr register name ffffe000h imc0 ffffe010h imc4 ffffe020h imc8 ffffe030h imcc 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h imc1 4h imc5 4h imc9 4h imcd 5h ditto 5h ditto 5h ditto 5h ditto 6h ditto 6h ditto 6h ditto 6h ditto 7h ditto 7h ditto 7h ditto 7h ditto 8h imc2 8h imc6 8h imca 8h imce 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch imc3 ch imc7 ch imcb ch imcf dh ditto dh ditto dh ditto dh ditto eh ditto eh ditto eh ditto eh ditto fh ditto fh ditto fh ditto fh ditto adr register name adr register name adr register name ffffe040h ivr ffffe060h intclr ffffe100h 1h ditto 1h ditto 1h 2h ditto 2h ditto 2h 3h ditto 3h ditto 3h 4h 4h 4h 5h 5h 5h 6h 6h 6h 7h 7h 7h 8h 8h 8h 9h 9h 9h ah ah ah bh bh bh ch ch ch ilev dh dh dh ditto eh eh eh ditto fh fh fh ditto
tmp19a64c1d tmp19a64 (rev1.1) -21-16 big-endian [11] dmac adr register name adr register name adr register name adr register name ffffe200h ccr0 ffffe210h bcr0 ffffe220h ccr1 ffffe230h bcr1 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h csr0 4h 4h csr1 4h 5h ditto 5h 5h ditto 5h 6h ditto 6h 6h ditto 6h 7h ditto 7h 7h ditto 7h 8h sar0 8h dtcr0 8h sar1 8h dtcr1 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch dar0 ch ch dar1 ch dh ditto dh dh ditto dh eh ditto eh eh ditto eh fh ditto fh fh ditto fh adr register name adr register name adr register name adr register name ffffe240h ccr2 ffffe250h bcr2 ffffe260h ccr3 ffffe270h bcr3 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h csr2 4h 4h csr3 4h 5h ditto 5h 5h ditto 5h 6h ditto 6h 6h ditto 6h 7h ditto 7h 7h ditto 7h 8h sar2 8h dtcr2 8h sar3 8h dtcr3 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch dar2 ch ch dar3 ch dh ditto dh dh ditto dh eh ditto eh eh ditto eh fh ditto fh fh ditto fh adr register name adr register name adr register name adr register name ffffe280h ccr4 ffffe290h bcr4 ffffe2a0h ccr5 ffffe2b0h bcr5 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h csr4 4h 4h csr5 4h 5h ditto 5h 5h ditto 5h 6h ditto 6h 6h ditto 6h 7h ditto 7h 7h ditto 7h 8h sar4 8h dtcr4 8h sar5 8h dtcr5 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch dar4 ch ch dar5 ch dh ditto dh dh ditto dh eh ditto eh eh ditto eh fh ditto fh fh ditto fh
tmp19a64c1d tmp19a64 (rev1.1) -21-17 big-endian adr register name adr register name adr register name adr register name ffffe2c0h ccr6 ffffe2d0h bcr6 ffffe2e0h ccr7 ffffe2f0h bcr7 1h ditto 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 3h ditto 4h csr6 4h 4h csr7 4h 5h ditto 5h 5h ditto 5h 6h ditto 6h 6h ditto 6h 7h ditto 7h 7h ditto 7h 8h sar6 8h dtcr6 8h sar7 8h dtcr7 9h ditto 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto bh ditto ch dar6 ch ch dar7 ch dh ditto dh dh ditto dh eh ditto eh eh ditto eh fh ditto fh fh ditto fh adr register name ffffe300h dcr 1h ditto 2h ditto 3h ditto 4h rsr 5h ditto 6h ditto 7h ditto 8h 9h ah bh ch dhr dh ditto eh ditto fh ditto
tmp19a64c1d tmp19a64 (rev1.1) -21-18 big-endian [12] cs/wait controller adr register name adr register name adr register name ffffe400h bma0 ffffe410h bma4 ffffe480h b01cs 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 4h bma1 4h bma5 4h b23cs 5h ditto 5h ditto 5h ditto 6h ditto 6h ditto 6h ditto 7h ditto 7h ditto 7h ditto 8h bma2 8h 8h b45cs 9h ditto 9h 9h ditto ah ditto ah ah ditto bh ditto bh bh ditto ch bma3 ch ch bexcs dh ditto dh dh ditto eh ditto eh eh ditto fh ditto fh fh ditto [13]access control [14] secur ity control [15] flash control adr register name adr register name adr register name ffffe500h ffffe510h dsusec1 ffffe520h flcs 1h 1h ditto 1h ditto 2h 2h ditto 2h ditto 3h pfbwait 3h ditto 3h ditto 4h 4h dsusec2 4h 5h 5h ditto 5h 6h 6h ditto 6h 7h 7h ditto 7h 8h 8h romsec1 8h 9h 9h 9h ah ah ah bh bh bh ch ch romsec2 ch dh dh dh eh eh eh fh fh fh [16] rom correction adr register name adr register name adr register name ffffe540h addreg0 ffffe550h addreg4 ffffe560h addreg8 1h ditto 1h ditto 1h ditto 2h ditto 2h ditto 2h ditto 3h ditto 3h ditto 3h ditto 4h addreg1 4h addreg5 4h addreg9 5h ditto 5h ditto 5h ditto 6h ditto 6h ditto 6h ditto 7h ditto 7h ditto 7h ditto 8h addreg2 8h addreg6 8h addrega 9h ditto 9h ditto 9h ditto ah ditto ah ditto ah ditto bh ditto bh ditto bh ditto ch addreg3 ch addreg7 ch addregb dh ditto dh ditto dh ditto eh ditto eh ditto eh ditto fh ditto fh ditto fh ditto
tmp19a64c1d tmp19a64 (rev1.1) -21-19 big-endian [17] clock timer adr register name adr register name ffffe700h rtcflg ffffe710h 1h ditto 1h 2h ditto 2h 3h ditto 3h 4h rtccr 4h 5h ditto 5h 6h ditto 6h 7h ditto 7h 8h rtcreg 8h 9h ditto 9h ah ditto ah bh ditto bh ch ch dh dh eh eh fh fh [18] cg adr register name adr register name adr register name ffffee00h syscr3 ffffee10h imcga ffffee20h eicrcg 1h syscr2 1h ditto 1h ditto 2h syscr1 2h ditto 2h ditto 3h syscr0 3h ditto 3h ditto 4h 4h imcgb 4h nmiflg 5h 5h ditto 5h ditto 6h 6h ditto 6h ditto 7h 7h ditto 7h ditto 8h 8h imcgc 8h 9h 9h ditto 9h ah ah ditto ah bh bh ditto bh ch ch imcgd ch dh dh ditto dh eh eh ditto eh fh fh ditto fh
TMP19A64C1DXBG 22. electrical characteristics the letter x in equations presented in this chapter represents the cycle peri od of the fsys clock selected through the programming of the syscr1.sysck bit. t he fsys clock may be derived from either the high-speed or low-speed crystal oscillat or. the programming of the clock gear function also affects the fsys frequency. all relevant values in this chapter are calculated with the high-speed (fc) system clock (syscr1.sysck = 0) and a clo ck gear factor of 1/fc (syscr1.gear[2:0] = 000). 22.1 absolute maximum ratings parameter symbol rating unit vcc2 (core) ? 0.3 to 3.0 vcc3 i/o ? 0.3 to 3.9 avcc a/d ? 0.3 to 3.9 supply voltage bvcc ? 0.3 to 3.9 v supply voltage v in ? 0.3 to v cc + 0.3 v per pin i ol 5 low-level output current total i ol 50 per pin i oh -5 high-level output current total i oh 50 ma power dissipation (ta = 85c) pd 600 mw soldering temperature (10 s) t solder 260 storage temperature t stg ? 40 to 125 except during flash w/e -20 to 85 operating temperature during flash w/e t opr 0 to 70 write/erase cycles n ew 100 cycle v cc15 dvcc15 cvcc15 fvcc15 v cc 3 dvcc3n n 0 to 4 avcc avcc3m m 1 to 2 v ss dvss avss cvss fvss note: the absolute maximum rating is a rating that must never be exceeded, even for an instant. not a single absolute maximum rating value can be exceeded. if any absolute maximum rating value is exceeded, the product may be damaged or weakened, or damage or combustion may cause personal injury. always be sure to design your application devices so the absolute maximum rating is never exceeded. 19a64(rev1.1)22-1
TMP19A64C1DXBG 22.2 dc electrical characteristics (1/3) ta 20 to 85 parameter symbol conditions min typ (note 1) max unit dvcc15 fosc = 8 to 13.5mhz fs = 30khz to 34khz fsys = 30khz to 54mhz plloff="1" 1.35 1.65 bvcc fsys = 16khz to 54mhz 1.8 3.3 supply voltage cvcc15 dvcc15 cvss dvss0v dvcc3n (n 0 to 4) fsys = 4 to 54mhz 1.65 3.3 v p7 to p9 (used as a port) v il1 2.7v Q avcc32Q avcc31Q 3.3v 0.3avcc31 0.3avcc32 1.65v Q dvcc3n Q 3.3v n=0 to 4 normal port v il2 1.8v Q bvcc Q 3.3v 0.3dvcc3n 0.3bvcc 1.65v Q dvcc3n Q 3.3v n=0 to 4 1.8v Q bvcc Q 3.3v 0.2dvcc3n 0.2bvcc schmitt-triggered port v il3 1.35v Q dvcc15 Q 1.65v 0.1dvcc15 x1 v il4 1.35v Q cvcc15 Q 1.65v 0.1cvcc low-level input voltage xt1 v il5 1.8v Q bvcc Q 3.3v ? 0.3 0.1cvcc v note1: bvcc normal mode 2.3v to 3.3v,backup mode 1.8v to 3.3v 19a64(rev1.1)22-2
TMP19A64C1DXBG ta 20 to 85 parameter symbol conditions min. typ (note 1) max. unit p7 to p9 (used as a port) v ih1 2.7v Q avcc32Q avcc31Q 3.3v 0.7avcc31 0.7avcc32 1.65v Q dvcc3n Q 3.3v n=0 to 4 normal port v ih2 1.8v Q bvcc Q 3.3v 0.7dvcc3n 0.7bvcc 1.65v Q dvcc3n Q 3.3v n=0 to 4 1.8v Q bvcc Q 3.3v 0.8dvcc3n 0.8bvcc schmitt-triggered port v ih3 1.35v Q dvcc15 Q 1.65v 0.9dvcc15 x1 v ih4 1.35v Q cvccQ 1.65v 0.9cvcc high-level input voltage xt2 v ih4 1.8v Q bvcc Q 3.3v 0.9bvcc dvcc3n + 0. 3 bvcc + 0.3 dvcc15 + 0. 2 cvcc+ 0.2 v i ol = 2ma dvcc3n R 2.7v 0.4 low-level output voltage v ol i ol = 500 a dvcc3n 2.7v 0.2dvcc3n Q0.4 i oh = ? 2ma dvcc3n R 2.7v 2.4 high-level output voltage v oh i oh = ? 500 a dvcc3n 2.7v 0.8dvcc3n v note 1: ta = 25c, dvcc15=1.5v,dvcc3n =3.0v, bvcc=3.0v, avcc3m=3.3v, unless otherwise noted 19a64(rev1.1)22-3
TMP19A64C1DXBG 22.3 dc electrical characteristics (2/3) ta 20 to 85 parameter symbol conditions min. typ (note 1) max. unit input leakage current i li 0.0 Q v in Q dvcc15 0.0 Q v in Q bvcc 0.0 Q v in Q dvcc3nn=0 to 4 0.0 Q v in Q avcc31 0.0 Q v in Q avcc32 0.02 5 output leakage current i lo 0.2 Q v in Q dvcc15 ? 0.2 0.2 Q v in Q bvcc ? 0.2 0.2 Q v in Q dvcc3n ? 0.2n=0 to 4 0.2 Q v in Q avcc31 ? 0.2 0.2 Q v in Q avcc32 ? 0.2 0.05 10 a v stop (dvcc15) 1.35 1.65 v stop1 (bvcc) 1.8 3.3 v stop2 (avcc3) v il1 = 0.3avcc31,32 v ih1 = 0.7avcc31,32 2.7 3.6 power-down voltage (stop mode ram backup) v stop3 (dvcc3) v il2 = 0.3dvcc3n, v il3 = 0.1dvcc3n v ih2 = 0.7dvcc3n, v ih3 = 0.9dvcc3n n=0 to 4 1.65 3.3 v pull-up resister at reset rrst dvcc15 = 1.5v 0.15v 20 50 150 k schmitt-triggered port vth 1.65vQdvcc3nQ3.3vn=0 to 4 1.8vQbvccQ3.3v 1.35vQdvcc15Q1.65v 0.3 0.6 v programmable pull-up/ pull-down resistor pkh dvcc3n = 1.65v to 3.3vn=0 to 4 dvcc15 = 1.35v to 1.65v bvcc = 1.8v to 3.3v 20 50 150 k pin capacitance (except power supply pins) c io fc = 1mhz 10 pf note 1: ta = 25c, dvcc15=1.5v,dvcc3n =3.0v, bvcc=3.0v, avcc3m=3.3v, unless otherwise noted 19a64(rev1.1)22-4
TMP19A64C1DXBG 22.4 dc electrical char acteristics (3/3) dvcc15 cvcc15 fvcc15 1.35v to 1.65v, dvcc3n fvcc3 2.7v to 3.3v, avcc3m 2.7v to 3.3v, bvcc=1.8v to 3.3v ta 20 to 85 n 0 to 4 m 1,2 parameter symbol conditions min. typ. (note 1) max. unit normal (note 2): gear = 1/1 50 60 idle(doze) 18 28 idle(halt) fsys = 54 mhz (fosc = 13.5 mhz, plloff="dvcc15") 14 23 ma slow fsys = 32.768khz (fs 32.768khz ) 300 970 a sleep fsys = 32.768khz (fs 32.768khz ) 100 950 a stop dvcc15 = cvcc15 = 1.35 to 1.65v bvcc 1.8 to 3.3v dvcc3n = 1.65 to 3.3v avcc3m = 2.7 to 3.3v 90 900 a backup icc bvcc 1.8 to 3.3v 3 5 a note 1: ta = 25c, dvcc15=1.5v,dvcc3n =3.0v, bvcc=3.0v, avcc3m=3.3v, unless otherwise noted note 2: measured with the cpu dhrystone operating, all i/o peripherals channel on, and 16-bit external bus operated with 4 system clocks. note 3: the supply current flowing through the dvcc15 bvcc dvcc3n cvcc15 and avcc3m pins is included in the digital supply current parameter (icc). 19a64(rev1.1)22-5
TMP19A64C1DXBG 22.5 10-bit adc electrical characteristics dvcc15 = cvcc15 = 1.35v to 1.65v, avcc3m = 2.7v to 3.3v, avss = dvss, ta 20 to 85 parameter symbol conditions min typ max unit 2.7 3.3 analog reference voltage ( + ) vrefh avcc3m ? 0.3 avcc avcc3m + 0.3 v analog reference voltage ( ? ) vrefl avss avss avss + 0 .2 v analog input voltage vain vrefl vrefh v a/d conversion avcc3m = vrefh = 3.0v 0.3v dvss = avss = vrefl 1.15 1.8 ma analog supply current non-a/d conversion iref avcc3m = vrefh = 2.7 to 3.3v dvss = avss = vrefl 0.1 10.0 a analog input capacitance ? 1.0 2.0 pf analog input impedance ? 2.0 3.5 k inl error ? 2 3 lsb dnl error ? 1 3 lsb offset error ? 2 3 lsb gain error ? avcc3m = vrefh = 3.0 v 0.3 v dvss = avss = vrefl ain resistance < 1.3k ain load capacitance < 20 pf avccm load capacitance 10 f vrefh load capacitance 10 f conversion time 7.85 s 2 4 lsb note 1: 1lsb = (vrefh ? vrefl)/1024[v] note 2: the supply current flowing through the avcc 3m pin is included in the digital supply current parameter (icc). 19a64(rev1.1)22-6
TMP19A64C1DXBG 22.6 ac electrical characteristics 1 separate bus mode (1)dvcc15 cvcc15 fvcc15 1.35v to 1.65v, dvcc3n fvcc3 2.3v to 3.3v syscr3 = ?0?, 2 programmed wait state equation 54 mhz (fsys) unit no. parameter symbol min max min max 1 system clock period (x) t sys 18.5 ns 2 a0-a23 valid to rd , wr or hwr asserted t ac (1+ale)x-20 17 ns 3 a0-a23 hold after rd , wr or hwr negated t car x-14 4.5 ns 4 a0-a23 valid to d0-d15 data in t ad x(2+tw+ale)-42 50.5 ns 5 rd asserted to d0-d15 data in t rd x(1+tw)-28 27.5 ns 6 rd width low t rr x(1+tw)-10 45.5 ns 7 d0-d15 hold after rd negated t hr 0 0 ns 8 negated to next a0-a23 output t rae x-15 3.5 ns rd 9 wr /hwr width low t ww x(1+tw)-10 45.5 ns 10 wr or hwr asserted to d0-d15 valid t do 12.3 12.3 ns 11 d0-d15 hold after wr or hwr negated t dw x(1+tw)-18 37.5 ns 12 d0-d15 hold after wr or hwr negated t wd x ? 1 5 3.5 ns 13 a0-a23 valid to wait input t aw x+(ale)x+(tw-1 )x -30 25.5 ns 14 wait hold after rd , wr or hwr asserted t cw x(tw-3)+7 x(tw-1)-17 25.5 38.5 ns note 1: no. 1 to 13 internal 2 wait insertion ale 1 clock @54mhz tw = (auto wait insertion + 2n) no. 14 conditions (auto wait insertion + 2n) tw = 2 + 2*1 = 4 ac measurement conditions: output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v 19a64(rev1.1)22-7
TMP19A64C1DXBG (2) dvcc15 cvcc15 fvcc15 1.35v to 1.65v, dvcc3n fvcc3 1.65v to 1.95v syscr3 = ?0?, 2programmed wait state equation 54 mhz (fsys) unit no. parameter symbol min max min max 1 system clock period (x) t sys 18.5 ns 2 a0-a23 valid to rd , wr or hwr asserted t ac (1+ale)x-20 17 ns 3 a0-a23 hold after rd , wr or hwr negated t car x-7 11.5 ns 4 a0-a23 valid to d0-d15 data in t ad x(2+tw+ale)-42 50.5 ns 5 rd asserted to d0-d15 data in t rd x(1+tw)-28 27.5 ns 6 rd width low t rr x(1+tw)-10 45.5 ns 7 d0-d15 hold after rd negated t hr 0 0 ns 8 negated to next a0-a23 output t rae x-15 3.5 ns rd 9 wr /hwr width low t ww x(1+tw)-10 45.5 ns 10 or hwr asserted to d0-d15 valid t do 12.3 12.3 ns wr 11 d0-d15 hold after wr or hwr negated t dw x(1+tw)-18 37.5 ns 12 d0-d15 hold after wr or hwr negated t wd x ? 1 5 3.5 ns 13 a0-a23 valid to wait input t aw x+(ale)x+(tw-1 )x -30 25.5 ns 14 wait hold after rd , wr or hwr asserted t cw x(tw-3)+7 x(tw-1)-17 25.5 38.5 ns note 1: no. 1 to 13 internal 2 wait insertion ale 1 clock @54mhz tw = (auto wait + 2n) no. 14 conditions (auto wait insertion + 2n) tw = 2 + 2*1 = 4 ac measurement conditions: output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v 19a64(rev1.1)22-8
TMP19A64C1DXBG (1) read cycle timing (syscr3 = 0, 1 programmed wait state) t car t rr t hr t ad internal clk rd t ac t rd a0~23 4clk/1bus cycle s1 s2 s0 s1 sw d0 15 d0~15 t rae cs0~3 r/w 19a64(rev1.1)22-9
TMP19A64C1DXBG (2) read cycle timing (syscr3 = 1, 1 programmed wait state) t car t rr t hr t ad t ad internalclk rd s1i s1 s2 s0 s1i d0 15 d0~15 t ac t rd a16~23 5clk/1bus cycle sw t rae cs0~3 r/w 19a64(rev1.1)22-10
TMP19A64C1DXBG (2) read cycle timing syscr3 = 1, 4 ex ternally generated wait states with n = 1) t aw internal clk rd a0~23 8clk/1bus cycle wait d0~15 d0 15 s1 sw swe sw s2 sw t cw cs0~3 r/w s1i s0 19a64(rev1.1)22-11
TMP19A64C1DXBG (4) write cycle timing (syscr3 = 1, zero wait sate) t ww t car t dw internal clk wr, hwr cs0~3 r/w t ac a0~23 4clk/1bus cycle t wd d0 15 d0~15 t do 19a64(rev1.1)22-12
TMP19A64C1DXBG 2 multiplex bus mode (1) dvcc15 cvcc15 fvcc15 1.35v to 1.65v, dvcc3n fvcc3 2.3v to 3.3v 1. ale width = 1 clock cycle, 2 programmed wait state equation 54 mhz (fsys) unit no. parameter symbo l min max min max 1 system clock period (x) t sys 18.5 ns 2 a0-a15 valid to ale low t al (ale)x-12 6.5 ns 3 a0-a15 hold after ale low t la x-8 10.5 ns 4 ale pulse width high t ll (ale)x-6 12.5 ns 5 ale low to rd , wr or hwr asserted t lc x-8 10.5 ns 6 rd , wr or hwr negated to ale high t cl x-15 3.5 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl 2x-20 17.0 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach 2x-20 17.0 ns 9 a16-a23 hold after rd , wr or hwr negated t car x-14 4.5 ns 10 a0-a15 valid to d0-d15 data in t adl x(2+tw+ale)-42 50.5 ns 11 a16-a23 valid to d0-d15 data in t adh x(2+tw+ale)-42 50.5 ns 12 rd asserted to d0-d15 data in t rd x(1+tw)-28 27.5 ns 13 rd width low t rr x(1+tw)-10 45.5 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x-15 3.5 ns 16 wr / hwr width low t ww x(1+tw)-10 45.5 ns 17 d0-d15 valid to wr or hwr negated t dw x(1+tw)-18 37.5 ns 18 d0-d15 hold after wr or hwr negated t wd x-15 3.5 ns 19 a16-a23 valid to wait input t awh x+(ale)x+(tw-1)x-3 0 25.5 ns 20 a0-a15 valid to wait input t awl x+(ale)x+(tw-1)x-3 0 25.5 ns 21 wait hold after rd , wr or hwr asserted t cw x(tw-3)+7 x(tw-1)-17 25.5 38.5 ns note 1: no. 1 to 20 internal 2 wait insertion ale 1 clock @54mhz tw = (auto wait insertion + 2n) no. 21 conditions (auto wait + 2n) tw = 2 + 2*1 = 4 ac measurement conditions: output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf 19a64(rev1.1)22-13
TMP19A64C1DXBG input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v (2) dvcc15 cvcc15 fvcc15 1.35v to 1.65v, dvcc3n fvcc3 1.65v to 1.95v ale width = 1 clock cycles, 2 programmed wait state equation 54 mhz (fsys) unit no. parameter symbo l min max min max 1 system clock period (x) t sys 18.5 ns 2 a0-a15 valid to ale low t al (ale)x-12 6.5 ns 3 a0-a15 hold after ale low t la x-8 10.5 ns 4 ale pulse width high t ll (ale)x-6 12.5 ns 5 ale low to rd , wr or hwr asserted t lc x-8 10.5 ns 6 rd , wr or hwr negated to ale high t cl x-15 3.5 ns 7 a0-a15 valid to rd , wr or hwr asserted t acl 2x-20 17.0 ns 8 a16-a23 valid to rd , wr or hwr asserted t ach 2x-20 17.0 ns 9 a16-a23 hold after rd , wr or hwr negated t car x-7 11.5 ns 10 a0-a15 valid to d0-d15 data in t adl x(2+tw+ale)-42 50.5 ns 11 a16-a23 valid to d0-d15 data in t adh x(2+tw+ale)-42 50.5 ns 12 rd asserted to d0-d15 data in t rd x(1+tw)-28 27.5 ns 13 rd width low t rr x(1+tw)-10 45.5 ns 14 d0-d15 hold after rd negated t hr 0 0 ns 15 rd negated to next a0-a15 output t rae x-15 3.5 ns 16 wr / hwr width low t ww x(1+tw)-10 45.5 ns 17 d0-d15 valid to wr or hwr negated t dw x(1+tw)-18 37.5 ns 18 d0-d15 hold after wr or hwr negated t wd x-15 3.5 ns 19 a16-a23 valid to wait input t awh x+(ale)x+(tw-1)x-3 0 25.5 ns 20 a0-a15 valid to wait input t awl x+(ale)x+(tw-1)x-3 0 25.5 ns 21 wait hold after rd , wr or hwr asserted t cw x(tw-3)+7 x(tw-1)-17 25.5 38.5 ns note 1: no. 1 to 20 internal 2 wait insertion ale 1 clock @54mhz tw = (auto insert wait + 2n) no. 21 conditions (auto 2 waits insertion + 2n) tw = 2 + 2*1 = 4 ac measurement conditions: output levels: high = 0.8dvcc33 v/low 0.2dvcc33 v, cl = 30 pf input levels: high = 0.7dvcc33 v/low 0.3dvcc33 v 19a64(rev1.1)22-14
TMP19A64C1DXBG (1) read cycle timing, ale width = 1 cl ock cycle, 1 programmed wait state t car t rr t hr t adh t adl t la d0 15 t al t cl t ll ale internal clk ad0~15 rd a0 15 t acl t ach t lc t rd a16~23 5clk/1bus cycle s1i s2 s3 s1 w1 t rae cs0~3 r/w s1 s2 s0 s1i sw 19a64(rev1.1)22-15
TMP19A64C1DXBG (2) read cycle timing, ale width = 1 cl ock cycle, 2 programmed wait state t car t rr t hr t adh t adl t la d0 15 t al t cl t ll ale internal clk ad0~1 5 rd a0 15 t acl t ach t lc t rd a16~2 3 6clk/1bus cycle t rae cs0~3 r/w 19a64(rev1.1)22-16
TMP19A64C1DXBG (3) read cycle timing, ale width = 1 cl ock cycle, 4 programmed wait state t awl/h ale internal clk ad0~15 rd a d16~23 8clk/1bus cycle wait d0 15 a0 15 t cw cs0~3 r/w 19a64(rev1.1)22-17
TMP19A64C1DXBG (4) read cycle timing, ale width = 2 cl ock cycle, 1 programmed wait state t rr t hr t adh t adl t la d0 15 t al t cl t ll ale internal clk ad0~15 rd s1i s1x sw s2 s0 a0 15 t acl t ach t lc t rd a16~23 6clk/1bus cycle s1 t rae cs0~3 r/w s1i 19a64(rev1.1)22-18
TMP19A64C1DXBG (5) read cycle timing, ale width = 2 cl ock cycle, 4 programmed wait state t awl/h ale internal clk ad0~15 rd ad16~23 9clk/1bus cycle wait d0 15 s1x s1 sw swex s0 a0 15 sw t cw cs0~3 r/w sw s2 s1x 19a64(rev1.1)22-19
TMP19A64C1DXBG (6) write cycle timing, ale width = 2 clock cycles, zero wait state t ww t car t dw t la d0 15 t al t cl t ll ale internal clk ad0~15 wr, hwr cs0~3 r/w a0 15 t acl t ach t lc ad16~23 5clk/1bus cycle t wd 19a64(rev1.1)22-20
TMP19A64C1DXBG (7) write cycle timing, ale width = 1 clock cycles, 2 wait state t ww t car t dw t la d0 15 t al t cl t ll al e internal clk ad0~1 5 wr, hwr cs0~ 3 r/ w a0 15 t acl t ach t lc ad16~2 3 6clk/1bus cycle t wd 19a64(rev1.1)22-21
TMP19A64C1DXBG (8) write cycle timing, ale width = 2 clock cycles, 4 wait state ale internal clk ad0~1 5 wr, hwr cs0~3 r/w ad16~2 3 9clk/1bus cycle t ww t car t dw t la d0 15 t al t cl t ll a0 15 t acl t ach t lc t wd wait t cw t awl/h 19a64(rev1.1)22-22
TMP19A64C1DXBG 22.7 transfer with dma request the following shows an example of a transfer between the on-chip ram and an external device in multiplex bus mode. ? 16-bit data bus width, non-recovery time ? level data transfer mode ? transfer size of 16 bits, devi ce port size (dps) of 16 bits ? source/destination: on-chip ram/external device the following shows transfer operation timing of the on-chip ram to an external bus during write operation (memory-to-memory transfer). gclkin dreqn a le hwr lwr a d[15:0] n transfer (n-1) transfer (n+1) transfe cs tdreq_w tdreq_w r/w a dd a dd a dd data data data gack 2clk 2clk ??? gbstart tdreq_r tdreq_r internal clock (1) indicates the condition under which nth transfer is performed successfully. (2) indicates the condition under which (n + 1)th transfer is not performed. 19a64(rev1.1)22-23
TMP19A64C1DXBG (1) dvcc15 cvcc15 fvcc15 1.35v to 1.65v, avcc3m fvcc3 2.7v to 3.3v dvcc33 2.3v to 3.3v, dvcc30/31/32/34 1.65v to 3.3v, ta 20 to 85 c m 1 to 2 equation 54 mhz (fsys) unit no. parameter symbol (1)min (2)max min max 2 rd asserted to dreqn negated (external device to on-chip ram transfer) tdreq_r w+1x 2wale8x 51 37 152.5 ns 3 wr / hwr rising to dreqn negated (on-chip ram to external device transfer) tdreq_w -(w+2)x 5+waitx51.8 -55.5 59.2 ns (2) dvcc15 cvcc15 fvcc15 1.35v to 1.65v, avcc3m =fvcc3 2.7v to 3.3v dvcc33 1.65v to 1.95v, dvcc30/31/32/34 1.65v to 3.3v, ta 20 to 85 c m 1 to 2 equation 54 mhz (fsys) unit no. parameter symbol (1)min (2)max min max 2 rd asserted to dreqn negated (external device to on-chip ram transfer) tdreq_r w+1 x 2w ale 8 x 56 37 147.5 ns 3 wr / hwr rising to dreqn negated (on-chip ram to external device transfer) tdreq_w -(w+2)x 5+waitx56.8 -55.5 54.2 ns w: number of wait-state cycles inserted. in the case of (2 + n) externally generated wait states with n = 1, w becomes 4 ale: apply ale = ale 1 clock, ale = 1 for ale 2 clock. the values in the above table are obtained with w = 1, ale = 1. 19a64(rev1.1)22-24
TMP19A64C1DXBG 22.8 serial channel timing (1) i/o interface mode (dvcc3n = 1.65v to 3.3v) in the table below, the letter x represents the fsys cycle period, which varies depending on the programming of the clock gear function. (1) sclk input mode (sio0 to sio6) equation 54 mhz parameter symbol min max min max unit sclk period t scy 12x 222 ns sclk clock high width(input) tsch 6x 111 ns sclk clock low width (input) tscl 6x 111 ns txd data to sclk rise or fall * t oss 2x-30 6 ns txd data hold after sclk rise or fall * t ohs 8x-15 129 ns rxd data valid to sclk rise or fall * t srd 30 30 ns rxd data hold after sclk rise or fall * t hsr 2x+30 66 ns * sclk rise or fall: measured relative to the programmed active edge of sclk. 2. sclk output mode (sio0 to sio6) equation 54 mhz parameter symbol min max min max unit sclk period t scy 8x 222 ns txd data to sclk rise or fall * t oss 4x-10 62 ns txd data hold after sclk rise or fall * t ohs 4x-10 62 ns rxd data valid to sclk rise or fall * t srd 45 45 ns rxd data hold after sclk rise or fall * t hsr 0 0 ns output data txd input data rxd sclk sck output mode/ active-high scl input mod 0 valid t oss t scy t ohs 1 2 3 t srd t hsr 0 1 2 3 valid valid valid sclk active-low sck input mode 19a64(rev1.1)22-25
TMP19A64C1DXBG 22.9 sbi timing (1) i2c mode in the table below, the letters x repr esent the fsys periods, respectively. n denotes the value of n programmed into the sck (scl output frequency select) field in the sbi0cr1. equation standard mode fast mode parameter symbol min max min max min max unit scl clock frequency t sc 0 0 100 0 400 khz hold time for start condition t hd:sta 4.0 0.6 s scl clock low width (input) (note 1) t low 4.7 1.3 s scl clock high width (output) (note 2) t high 4.0 0.6 s setup time for a repeated start condition t su;sta (note 5) 4.7 0.6 s data hold time (input) (note 3, 4) t hd;dat 0.0 0.0 s data setup time t su;dat 250 100 ns setup time for stop condition t su;sto 4.0 0.6 s bus free time between stop and start conditions t buf (note 5) 4.7 1.3 s note 1: scl clock low width (output) is calculated with : (2 n-1 +58)/(fsys/2) note 2: scl clock high width (output) is calculated with (2 n-1 +12)/(fsys/2) notice: on i 2 c-bus specification, maximum speed of standard mode is 100khz ,fast mode is 400khz. internal scl clock frequency setti ng should be shown above note1 & note2. note 3: the output data hold time is equal to 12x note 4: the philips i 2 c-bus specification states t hat a device must internally provide a hold time of at least 300 ns for the sda signal to bridge the undefined region of the fall edge of scl. however, the 19a64 sbi does not satisfy this requirement. also, the output buffer for scl does not incorporate slope control of the falli ng edges; therefore, the equipment manufacturer should design so that the input data hold time sh own in the table is satisfied, including tr/tf of the scl and sda lines. note 5: software-dependent sda scl t low t hd;sta t scl t high t r t su;dat t hd;dat t su;sta t su;sto t buf s: start condition sr: repeated start condition p: stop condition t f s sr p 19a64(rev1.1)22-26
TMP19A64C1DXBG (2) clock-synchronous 8-bit sio mode in the tables below, the letters x represent t he fsys cycle periods, respectively. the letter n denotes the value of n programmed into the sck (scl output frequency select) field in the sbi0cr1. the electrical specifications below are for an sck signal with a 50% duty cycle. sck input mode equation 54 mhz parameter symbol min max min max unit sck period t scy 16x 296 ns so data to sck rise t oss (t scy /2) ? ( 6 x + 3 0 ) 7 ns so data hold after sck rise t ohs (t scy /2) + 4x 222 ns si data valid to sck rise t srd 0 0 ns si data hold after sck rise t hsr 4x + 10 84 ns sck output mode equation 54 mhz parameter symbol min max min max unit sck period (programmable) t scy 16x 296 ns so data to sck rise t oss (t scy /2) ? 20 128 ns so data hold after sck rise t ohs (t scy /2) ? 20 128 ns si data valid to sck rise t srd 2x + 30 67 ns si data hold after sck rise t hsr 0 0 ns output data txd input data txd sclk 0 valid t oss t scy t ohs 1 2 3 t srd t hsr 0 1 2 3 valid valid valid 19a64(rev1.1)22-27
TMP19A64C1DXBG 22.10 event counter in the table below, the letter x represents the fsys cycle period. equation 54 mhz parameter symbol min max min max unit clock low pulse width t vckl 2x + 100 137 ns clock high pulse width t vckh 2x + 100 137 ns 22.11 timer capture in the table below, the letter x represents the fsys cycle period. equation 54 mhz parameter symbol min max min max unit low pulse width t cpl 2x + 100 137 ns high pulse width t cph 2x + 100 137 ns 22.12 general interrupts in the table below, the letter x represents the fsys cycle period. equation 54 mhz parameter symbol min max min max unit low pulse width for int0-inta t intal x + 100 118.5 ns high pulse width for int0-inta t intah x + 100 118.5 ns 22.13 nmi and stop /sleep wake-up interrupts equation 54 mhz parameter symbol min max min max unit low pulse width for nmi and int0-int4 t intbl 100 100 ns high pulse width for int0-int4 t intbh 100 100 ns 22.14 scout pin equation 54 mhz parameter symbol min max min max unit clock high pulse width t sch 0.5t ? 5 4.25 ns clock low pulse width t scl 0.5t ? 5 4.25 ns note: in the above table, the letter t represent s the cycle period of t he scout output clock. t sch t scl scout 19a64(rev1.1)22-28
TMP19A64C1DXBG 22.15 bus request and bus acknowledge signals t aba (note1) busrq a le a 0~a23, rd , wr busak cs0 ~ cs3 , w/r , hwr a d0~ad15 t baa (note2) (note2) equation 54 mhz parameter symbol min max min max unit bus float to busak asserted t aba 0 80 0 80 ns bus float after busak negated t baa 0 80 0 80 ns note 1: if the current bus cycle has not terminated due to wait-state insertion, the tmp19a64f20bxbg does not respond to busrq until the wait state ends. note 2: this broken line indicates that output buffers are disabled, not that the signals are at indeterminate states. the pin holds the last logic value present at that pin before the bus is relinqu ished. this is dynamically accomplished through external load capacitances. the equipment manufacturer may maintain the bus at a predefined state by means of off-chip restores, but he or she should design, considering the time (determined by the cr constant) it takes for a signal to reach a des ired state. the on-chip, integrated programmable pullup/pulldown resistors remain active, depending on internal signal states. 19a64(rev1.1)22-29
TMP19A64C1DXBG 22.16 kwup input pull-up register active equation 54 mhz parameter symbol min max min max unit low pulse width for key0-d tky tbl x+100 118 ns high pulse width for key0-d tky tbh x+100 118 ns 22.17 dual pulse input equation 54 mhz parameter symbol min max min max unit dual input pulse period tdcyc 8y 296 ns dual input pulse setup tabs y20 57 ns dual input pulse hold tabh y20 57 ns y: sampling clock (fsys/2) tabs tdc y c tabh a b 19a64(rev1.1)22-30
TMP19A64C1DXBG tmp19a64(rev1.1)-23-1 23. notations, precautions and restrictions 23.1 notations and terms (1) i/o register fields ar e often referred to as . for the interest of brevity. for example, trun.t0run means the t0run bit in the trun register. (2) fc, fsys, state fosc: clock supplied from the x1 and x2 pins fpll: clock generated by the on-chip pll fc: clock selected by the plloff pin fgear: clock selected by the syscr1.gear[1:0] bits fsys: clock selected by the syscr1.sysck bit the fsys cycle is referred to as a state. in addition, the clock selected by the syscr1.fpsel bit and the prescaler clock source selected by the syscr0.prck[1:0] bits are referred to as fperiph and t0 respectively. 23.2 precautions and restrictions (1) processor revision identifier the process revision identifier (prid) register in the tx19a core of the tmp19a64c1d contains 0x0000_2ca1. (2) bw0?bw1 pins the bw0 and bw1 pins must be connected to the dvcc2 pin to ensure that their signal levels do not fluctuate during chip operation. (3) oscillator warm-up counter if an external crystal is utilized, an interrupt signal programmed to bring the tmp1940cyaf out of stop mode triggers the on-chip warm-up counter. the system clock is not supplied to the on-chip logic until the warm-up counter expires. (4) programmable pullup resistors when port pins are configured as input ports, the integrated pull-up resistors can be enabled and disabled under software control. the pull-up resistors are not programmable when port pins are configured as output ports. the relevant port registers are pr ogrammed with the data resister. (5) external bus mastership the pin states while the bus is granted to an external device are described in chapter 7, i/o ports . (6) watchdog timer (wdt) upon reset, the wdt is enabled. if the watchdog timer function is not required, it must be disabled after reset. when relevant pins are configured as bus ar bitration signals, the i/o peripherals including the wdt can operate during exte rnal bus mastership. (7) a/d converter (adc) the ladder resistor network between the vrefh and vrefl pins can be disconnected under software control. this helps to reduce power dissipation, for example, in stop mode.
TMP19A64C1DXBG tmp19a64(rev1.1)-23-2 (8) undefined bits in i/o registers undefined i/o register bits are read as undefined states. therefore, software must be coded without relying on the states of any undefined bits. (9) electrostatic discharge (esd) sensitivity the following shows esd sensitivity. protect the device from static damage during device development or production stage. for a detailed description on esd, see general safety precautions and usage considerations. ? TMP19A64C1DXBG specification sensitivity machine model: mm 200 v human body model: hbm 1750v 2000 v ? tmp19a64f20axbg specification sensitivity machine model: mm 200 v human body model: hbm 2000v 2000 v (10) bus access of debug mode ( mask product only) bus accessing is abnormal for external function with sreq mode in debug mode, which means debug=?1? in cp0 register. of mask type mcu ,TMP19A64C1DXBG. pls don?t access to external function with sreq mode in debug mode.
TMP19A64C1DXBG tmp19a64(rev1.1)-23-3 (11) notations, precautions and restrictions overflow exception problem: if an overflow exception caused a jump to the exception handler and the first instruction in that exception handler caused another exception, the epc register should point to the address of the first instruction in the exception handler. however, the epc re gister might contain the address th at caused the overflow exception. ? problem-causing situation: when, with the instruction pipeline full, an overflow exception was taken at the following sequence of instructions and then the first instruction in the overflow exception handler causes another exception add, addi or sub <= # instruction that causes an overflow jump or branch instruction <= # instruction with a delay slot delay slot note: toshiba?s compiler uses no instructions that could cause an overflow. therefore, this problem does not occur. workaround: don?t place a jump or branch inst ruction immediately following an instruction that could cause an overflow (add, addi or sub).
TMP19A64C1DXBG tmp19a64(rev1.1)-23-4 lwl and lwr instructions problem: the lwl or lwr instruction might provide incorrect results. ? problem-causing situation #1: a. the destination of a load instruction (lb, lbu, lh, lhu, lw, lwl or lwr) is identical to that of the lwl or lwr instruction. b. the instruction pipeline is full. (the load in struction and the lwl or lwr instruction will be executed consecutively.) c. the dmac is programmed for data cache snooping. once the load instruction is executed, the dmac initiates a dma transaction. after it has been serviced, the lwl or lwr instruction is executed. this problem occurs when all of these conditions are true. ? problem-causing situation #2: a. the destination of a load instruction (lb, lbu, lh, lhu, lw, lwl or lwr) is identical to that of the lwl or lwr instruction. b. the doze or halt bit in the config register is set to 1 immediately before the load instruction. c. the instruction pipeline is full. (the load in struction and the lwl or lwr instruction will be executed consecutively.) d. after the load instruction is executed, the processor is put in the stop, sleep or idle mode. e. after an interrupt signaling brings the processor out of the stop, sleep or idle mode, the lwl or lwr instruction is executed. note: this applies to the case in which an interrupt signaling does not generate an interrupt upon exit from stop or idle mode. in other words, either the iec bit in the status register is cleared (interrupts disabled), or if the iec bit is set, the priority level of the incoming interrupt signaling is lower than the mask level programmed in the cmask field in the status register. (exit from stop, sleep or idle mode can be accomplished even with such settings.) this problem occurs when all of these conditions are true. workarounds: to use the lwl or lwr instruction, 1) place a nop between a load instructio n and the lwl or lwr instruction, or 2) disable the data cache snooping of the dmac be fore the lwl or lwr instruction is executed. also, do not put the processor in stop, s leep or idle mode before the lwl or lwr instruction is executed.
TMP19A64C1DXBG tmp19a64(rev1.1)-23-5 overflow exception when a dsu probe is used problem: it looks as if an overflow exception caused a jump to the reset and nonmaskable exception vector address (0xbfc0_0000). ? problem-causing situation: when an overflow exception occurs, with the processor connected to a dsu probe note: toshiba?s compiler uses no instructions that could cause an overflow. therefore, this problem does not occur. workaround: don?t place a jump or branch inst ruction immediately following an instruction that could cause an overflow (add, addi or sub). malfunction of using busreq signl in external bus access mode [condition] in external bus mode, using auto wait insert function (as same as +n wait) use external bus request signal function (busreq). for each target product,bus setting mode (multiplex/ separate) ale width(short/long) . please refer to following table. internal clock ale output (ale=1.5clk) rd output ( normal ) rd output (abnormal ) s0 s1 w1 w2 w3 s2 s3 trd spec not achieve because of 1 minus wait from original insert external bus request (busreq) when starting bus cycle (s0) s0 s1 w1 w2 s2 s3 (exp: ale band =1.5clk, auto wait = 3 )